Freescale Semiconductor Document Number: PXS30 Rev. 1, 09/2011 Data Sheet: Advance Information PXS30 PXS30 Microcontroller Data 473 MAPBGA 257 MAPBGA Sheet (19 x 19 mm) (14 x 14 mm) 1 Introduction . 2 The PXS30 family represents a new generation of 1.1 Document overview 2 32-bit microcontrollers based on the Power 1.2 Device comparison . 2 1.3 Block diagram . 4 Architecture . These devices provide a 1.4 Feature list . 6 cost-effective, single chip display solution for the 1.5 Feature details 7 industrial market. An integrated TFT driver with 2 Package pinouts and signal descriptions 19 2.1 Package pinouts 19 digital video input ability from an external video 2.2 Pin descriptions 22 source, significant on-chip memory, and low power 3 Electrical characteristics . 70 3.1 Introduction 70 design methodologies provide flexibility and 3.2 Absolute maximum ratings 70 reliability in meeting display demands in rugged 3.3 Recommended operating conditions 71 environments. The advanced processor core offers 3.4 Thermal characteristics 73 3.5 Electromagnetic interference (EMI) characteristics . 74 high performance processing optimized for low 3.6 Electrostatic discharge (ESD) characteristics 75 power consumption, operating at speeds as high as 3.7 Static latch-up (LU) 75 3.8 Power Management Controller (PMC) electrical 64 MHz. The family itself is fully scalable from characteristics . 76 512 KB to 1 MB internal flash memory. The 3.9 Supply current characteristics . 78 memory capacity can be further expanded via the 3.10 Temperature sensor electrical characteristics . 78 3.11 Main oscillator electrical characteristics 79 on-chip QuadSPI serial flash controller module. 3.12 FMPLL electrical characteristics 79 3.13 16 MHz RC oscillator electrical characteristics 81 The PXS30 family platform has a single level of 3.14 ADC electrical characteristics 81 memory hierarchy supporting on-chip SRAM and 3.15 Flash memory electrical characteristics 87 3.16 SRAM memory electrical characteristics . 89 flash memories. The 1 MB flash version features 3.17 GP pads specifications . 89 160 KB of on-chip graphics SRAM to buffer cost 3.18 PDI pads specifications 91 effective color TFT displays driven via the on-chip 3.19 DRAM pad specifications . 96 3.20 RESET characteristics 102 Display Control Unit (DCU). See Table 1 for 3.21 Reset sequence . 102 specific memory size and feature sets of the product 3.22 Peripheral timing characteristics . 110 4 Package characteristics 132 family members. 4.1 Package mechanical data 132 5 Orderable parts 137 The PXS30 family benefits from the extensive 6 Reference documents . 137 development infrastructure for Power Architecture 7 Document revision history 138 devices, which is already well established. This includes full support from available software drivers, operating systems, and configuration code This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. Freescale Semiconductor, Inc., 2011. All rights reserved. PreliminarySubject to Change Without NoticeIntroduction to assist with users implementations. See Section 3, Developer support, for more information. 1 Introduction 1.1 Document overview This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the devices. This document provides electrical specifications, pin assignments, and package diagrams for the PXS30 series of microcontroller units (MCUs). For functional characteristics, see the PXS30 Microcontroller Reference Manual. 1.2 Device comparison Table 1. PXS30 Family Feature Set Features PXS3010 PXS3015 PXS3020 1 CPU Type 2 e200z7d (SoR ) in lock-step or decoupled operation Architecture Harvard Execution speed 0150 MHz (+2% FM) 0180 MHz (+2% FM) 0180 MHz (+2% FM) Nominal platform 075 MHz (+2% FM) 090 MHz (+2% FM) 090 MHz (+2% FM) frequency (in 1:1, 1:2, and 1:3 modes) MMU 64 entries (SoR) Instruction set PPC Yes Instruction set VLE Yes Instruction cache 16 KB, 4-way with EDC (SoR) Data cache 16 KB, 4-way with EDC (SoR) MPU Yes (SoR) Buses Core bus 32-bit address, 64-bit data Internal periphery bus 32-bit address, 32-bit data XBAR Master slave ports Yes (SoR) Memory Static RAM (SRAM) 256 KB (ECC) 384 KB (ECC) 512 KB (ECC) 2 2 2 Code Flash memory 1MB 1.5MB 2MB 2 Data Flash memory 64 KB PXS30 Microcontroller Data Sheet, Rev. 1 2 PreliminarySubject to Change Without Notice Freescale Semiconductor