Freescale Semiconductor Document Number: MSC8157 Data Sheet: Technical Data Rev. 3, 12/2013 MSC8157 MSC8157 Six-Core Digital Signal Processor FC-PBGA783 29 mm x 29 mm Six StarCore SC3850 DSP subsystems, each with an High-speed serial interface with a 10-lane SerDes PHY that SC3850 DSP core, 32 KB L1 instruction cache, 32 KB L1 supports two Serial RapidIO interfaces, one PCI Express data cache, unified 512 KB L2 cache configurable as M2 interface, six CPRI lanes, and two SGMII interfaces memory in 64 KB increments, memory management unit (multiplexed). The Serial RapidIO interfaces support (MMU), extended programmable interrupt controller x1/x2/x4 operation up to 5 Gbaud with an enhanced (EPIC), two general-purpose 32-bit timers, debug and messaging unit (eMSG) and two DMA units. The PCI profiling support, low-power Wait, Stop, and power-down Express controller supports 32- and 64-bit addressing, processing modes, and ECC/EDC support. x1/x2/x4 link. The six CPRI controllers can support six Chip-level arbitration and switching system (CLASS) that lanes up to 6.144 Gbaud. provides full fabric non-blocking arbitration between the QUICC Engine technology subsystem with dual RISC cores and other initiators and the M2 memory, shared M3 processors, 48 KB multi-master RAM, 48 KB instruction memory, DDR SRAM controller, device configuration RAM, supporting two communication controllers for two control and status registers, MAPLE-B, and other targets. Gigabit Ethernet interfaces (RGMII or SGMII), to offload 3072 KB 128-bit wide M3 memory, 2048 KBs of which scheduling tasks from the DSP cores, and an SPI. can be turned off to save power. I/O Interrupt Concentrator consolidates all chip maskable 96 KB boot ROM. interrupt and non-maskable interrupt sources and routes Three input clocks (one global and two differential). then to INT OUT/CP TX INT, NMI OUT/CP RX INT, Six PLLs (three global, two Serial RapidIO, one DDR and the cores. PLLs). UART that permits full-duplex operation with a bit rate of Second generation Multi-Accelerator Platform Engine for up to 6.25 Mbps. Baseband (MAPLE-B2) with a second generation Two general-purpose 32-bit timers for RTOS support per programmable system interface (PSIF2) Turbo encoding SC3850 core, four timer modules with four 16-bit fully and decoding Viterbi decoding FFT/iFFT and DFT/iDFT programmable timers, two timer modules with four 32-bit processing downlink chip rate processing CRC fully programmable timers and eight software watchdog processing and insertion equalization processing and timers (SWT). matrix inversion uplink batch and fast processing. Some Eight programmable hardware semaphores. MAPLE-B2 processors can be disabled when not required Up to 32 virtual interrupts and a virtual NMI asserted by to reduce overall power consumption. simple write access. 2 One DDR controllers with up to a 667 MHz clock (1333 I C interface. MHz data rate), 64/32 bit data bus, supporting up to a total Up to 32 GPIO ports, sixteen of which can be configured as 2 Gbyte in up to four banks (two per controller) and support external interrupts. for DDR3. Boot interface options include Ethernet, Serial RapidIO 2 DMA controller with 32 unidirectional channels interface, I C, and SPI. supporting 16 memory-to-memory channels with up to Supports IEEE Std. 1149.6 JTAG interface 1024 buffer descriptors per channel, and programmable Low power CMOS design, with low-power standby and priority, buffer, and multiplexing configuration. It is power-down modes, and optimized power-management optimized for DDR SDRAM. circuitry. 45 nm SOI CMOS technology. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 20102013 Freescale Semiconductor, Inc. All rights reserved.Table of Contents 1 Block Diagram .3 3.5 DC Electrical Characteristics 54 2 Pin Assignment .4 3.6 AC Timing Characteristics 69 2.1 FC-PBGA Ball Layout Diagram 4 4 Hardware Design Considerations . 92 2.2 Signal Lists .5 5 Ordering Information . 92 3 Electrical Characteristics 52 6 Package Information . 93 3.1 Maximum Ratings .52 7 Product Documentation . 94 3.2 Recommended Operating Conditions 53 8 Revision History 95 3.3 Thermal Characteristics 54 3.4 CLKIN/MCLKIN Requirements .54 MSC8157 Six-Core Digital Signal Processor Data Sheet, Rev. 3 2 Freescale Semiconductor