MVF60NN151CMK40 NXP

Document Number VYBRIDFSERIESEC NXP Semiconductors Rev. 9, 01/2018 Data Sheet: Technical Data VYBRIDFSERIESEC VF6xx, VF5xx, VF3xx Features Debug Standard JTAG Operating characteristics 16-bit Trace port Voltage range 3 V to 3.6 V Temperature range(ambient) -40 C to 85 C Timers Motor control/general purpose timer (FTM) ARM Cortex A5 Core features Periodic Interrupt Timers (PITs) Up to 500 MHz ARM Cortex A5 Low-power timer (LPTMR0) 32 KB/32 KB I/D L1 Cache IEEE 1588 Timer per MAC interface (part of 1.6 DMIPS/MHz based on ARMv7 architecture Ethernet Subsystem) NEON MPE (Media Processing Engine) Co- processor Communications Double Precision Floating Point Unit Six Universal asynchronous receivers/transmitters 512 KB L2 cache (on selected part numbers only) (UART)/Serial communications interface (SCI) with LIN, ISO7816, IrDA, and hardware flow control ARM Cortex M4 Core features Four Deserial Serial peripheral interface (DSPI) Up to 167 MHz ARM Cortex M4 Four Inter-Integrated Circuit (I2C) with SMBUS Integrated DSP capability support 64 KB Tightly Coupled Memory (TCM) Dual USB OTG Controller + PHY 16 KB/16 KB I/D L1 Cache Dual 4/8 bit Secure Digital Host controller 1.25 DMIPS/MHz based on ARMv7 architecture Dual 10/100 Ethernet with L2 Switch (IEEE 1588) Clocks Dual FlexCAN3 24 MHz crystal oscillator Security 32 kHz crystal oscillator ARM TrustZone including the TZ architecture Internal reference clocks (128 KHz and 24 MHz) Cryptographic Acceleration and Assurance Module, Phase Locked Loops (PLLs) incorporates 16 KB secure RAM (CAAM) Low Jitter Digital PLLs Secure Non-Volatile Storage, including Secure Real System debug, protection, and power management Time Clock (SNVS) Various stop, wait, and run modes to provide low Real Time Integrity Checker (RTIC) power based on application needs Tamper detection - supported by external pins, on- Peripheral clock enable register can disable clocks to chip clock monitors, voltage and temperature unused modules, thereby reducing currents tampers Low voltage warning and detect with selectable trip TrustZone Watchdog (TZ WDOG) points Trust Zone Address Space Controller Illegal opcode and illegal address detection with Central Security Unit programmable reset or processor exception response Secure JTAG Hardware CRC module to support fast cyclic High Assurance Boot (HAB) with support for redundancy checks (CRC) encrypted boot 128-bit unique chip identifier Memory Interfaces Hardware watchdog 8/16 bit DRAM Controller with support for External Watchdog Monitor (EWM) LPDDR2/DDR3 - Up to 400 MHz (ECC supported Dual DMA controller with 32 channels (with for 8-bit only and not 16-bit) DMAMUX) 8/16 bit NAND Flash controller with ECC 8/16/32 bit External bus (Flexbus) Dual Quad SPI with XIP (Execute-In-Place) NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. Display and Video Dual Display Control Unit (DCU) with support for color TFT display up to SVGA Segmented LCD (3V Glass only) configurable as 40x4, 38x8, and 36x6 Video Interface Unit (VIU) for camera Open VG Graphics Processing Unit (GPU) VideoADC Analog Dual 12-bit SAR ADC with 1MS/s Dual 12-bit DAC Audio Four Synchronous Audio Interface (SAI) Enhanced Serial Audio Interface (ESAI) Sony Philips Digital Interface (SPDIF), Rx and Tx Asynchronous Sample Rate Converter (ASRC) Human-Machine Interface (HMI) GPIO pins with interrupt support, DMA request capability, digital glitch filter. Hysteresis and configurable pull up/down device on all input pins Configurable slew rate and drive strength on all output pins On-Chip Memory 512 KB On-chip SRAM with ECC 1 MB On-chip graphics SRAM (no ECC). This depends on the part selected. Alternate configuration could be 512 KB graphics and 512 KB L2 cache. 96 KB Boot ROM VF6xx, VF5xx, VF3xx, Rev. 9, 01/2018 2 NXP Semiconductors