N74F02N,602 NXP

INTEGRATED CIRCUITS 74F02 Quad 2-input NOR gate Product specification 1990 Oct 04 IC15 Data Handbook Philips Semiconductors Product specification Quad 2-input NOR gate 74F02 FEATURE PIN CONFIGURATION Industrial temperature range available (40C to +85C) Q0 1 14 V CC D0a 2 13 Q3 TYPE TYPICAL TYPICAL SUPPLY D0b 3 12 D3b PROPAGATION CURRENT DELAY (TOTAL) Q1 4 11 D3a 74F02 3.4ns 4.4mA D1a 5 10 Q2 D1b 6 9 D2a GND 7 8 D2b SF00007 ORDERING INFORMATION ORDER CODE DESCRIPTION PKG DWG COMMERCIAL RANGE INDUSTRIAL RANGE V = 5V 10%, T = 0C to +70C V = 5V 10%, T = 40C to +85C CC amb CC amb 14-pin plastic DIP N74F02N I74F02N SOT27-1 14-pin plastic SO N74F02D I74F02D SOT108-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Dna, Dnb Data inputs 1.0/1.0 20A/0.6mA Qn Data output 50/33 1.0mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20A in the high state and 0.6mA in the low state. LOGIC DIAGRAM FUNCTION TABLE 2 D0a INPUTS OUTPUT 1 3 Q0 D0b Dna Dnb Qn 5 D1a 4 L L H 6 Q1 D1b L H L 8 D2a 10 Q2 9 H L L D2b H H L 11 V = Pin 14 13 D3a CC Q3 12 GND = Pin 7 NOTES: D3b 1 H = High voltage level SF00008 2 L = Low voltage level LOGIC SYMBOL IEC/IEEE SYMBOL 2 3 56 89 11 12 1 2 1 3 D0a D0bD1a D1bD2a D2b D3a D3b 5 4 6 Q0 Q1 Q2 Q3 8 V = Pin 14 10 CC 1 4 10 13 GND = Pin 7 9 SF00009 11 13 12 SF00010 1990 Oct 04 2 853-0326 00622