UM10736 LPC15xx User manual Rev. 1.2 28 December 2017 User manual Document information Info Content Keywords LPC1500, LPC1500 User manual , LPC15xx UM, LPC1549, LPC1548, LPC1547, LPC1519, LPC1518, LPC1517 Abstract LPC15xx User manualUM10736 NXP Semiconductors LPC15xx User manual Revision history Rev Date Description 1.2 20171228 LPC15xx User manual Modifications: Section 27.7.5.2 Calculating the C CAN bit rate added. IAP entry location corrected in Section 34.9 IAP commands. Bit description of AUTOBAUD bit updated in Table 348 USART Control register (CTL, address 0x4004 0004 (USART0), 0x4004 4004 (USART1), 0x400C 0004 (USART2)) bit description: This bit can only be set when UART is enabled in the CFG register and is cleared when the UART is disabled. Clarified clock settings in the ADC CONFIG T structure of the ADC API (Section 42.4.12.1 ADC CONFIG T channel configuration structure): system clock >= adc clock. Embedded Trace Macrocell (ETM) support clarified in Section 43.2. This feature is not available. Watchdog interrupt flag polarity corrected: This flag is cleared by writing a 1 to the WDINT bit in the MOD register (Section 17.6.1 Watchdog mode register). Use of power profiles with IAP commands clarified. See Section 34.9 and Section 35.2. CCLK parameter in IAP calls replaced by NULL. See Section 34.9 IAP commands. For autobaud, set BRG to 0x0 (default value). Section 24.7.5. Section 24.7.5 Autobaud function corrected (clearance of AUTOBAUD bit). The IREF PD in the PDRUNCFG register must be turned on to use the comparator. See Table 75 Power configuration register (PDRUNCFG, address 0x4007 4208) bit description, Table 74 Wake-up configuration register (PDAWAKECFG, address 0x4007 4204) bit description, and Section 29.3. VREFP/VERFN voltage selection requirements added in Section 28.4. RTC oscillator 32 kHz frequency clarified in Chapter 18 (exact frequency is 32.768 kHz). Added text after Table 344 Endpoint commands: For EP0 transfers, the hardware will do auto handshake as long as the ACTIVE bit is set in EP0 IN/OUT command list. Unlike other endpoints, the hardware will not clear the ACTIVE bit after transfer is done. Thus, the software should manually clear the bit whenever it receives new setup packet and set it only after it has queued the data for control transfer. Changed the bit field name in QEI Digital filter on index input register from FITLINX to FILTINX. See Table 315 QEI Digital filter on index input register (FILTERINX, 0x4005 8044) bit description Updated Figure 1 Memory mapping. Changed base address of C CAN peripheral to 0x400E 0000. Deleted duplicate entry of the list UART transmit and receive functions can be operated with the system DMA controller. See Section 24.2 Features. Changed: REGMODEn = 0: Registers operate as match and reload registers and REGMODEn = 1: Registers operate as capture and capture control registers. See Section 15.6 Register description and Section 16.6 Register description. Updated Table 36 Peripheral reset control register 1 (PRESETCTRL1, address 0x4007 4048) bit description: Bit 28 is reserved. Removed references to WRAPEN field from Table 434 ADC Input Select Register (INSEL, addresses 0x4000 0004 (ADC0) and 0x4008 0004 (ADC1)) bit description. Added a remark to Table 216 SCT DMA 0 request register (DMAREQ0, address 0x1C01 805C) bit description and Table 217 SCT DMA 1 request register (DMAREQ1, address 0x1C01 8060) bit description. Added a remark to Table 249 SCT DMA 0 request register (DMAREQ0, address 0x1C02 005C (SCT2) and 0x1C02 405C (SCT3)) bit description and Table 250 SCT DMA 1 request register (DMAREQ1, address 0x1C02 0060 (SCT2) and 0x1C02 4060 (SCT3)) bit description. Fixed typographical errors in Chapter 15 Large SCTimer/PWM (SCTimer0/PWM, SCTimer1/PWM) and Chapter 16 Small SCTimer/PWM (SCTimer2/PWM, SCTimer3/PWM). Changed SCTIPU ABORT to SCTIPU ABORT0, SCTIPU ABORT1, and SCTIPU ABORT2. See Table 127, Table 128, and Table 129. UM10736 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.2 28 December 2017 2 of 765