QorIQ Communications Platforms P Series QorIQ P1015 and P1024 communications processors The P1015 and P1024 processors are the two QorIQ platforms deliver an impressive Overview perfectly suited for multi-service gateways, 4.5x aggregate frequency range. Freescale QorIQ communications platforms are Ethernet switch controllers, wireless LAN the next-generation evolution of our leading The P1015 and P1024 platforms both feature access points and high-performance general- PowerQUICC communications processors. the e500 Power Architecture core and purpose control processor applications with Built using high-performance Power peripherals, and are fully software compatible tight thermal constraints. Architecture cores, QorIQ platforms enable with the existing PowerQUICC processors. This a new era of networking innovation where the The P1015 and P1024 processors are pin- enables you to create a product with multiple reliability, security and quality of service for compatible with the QorIQ P1016, P1025 performance points with a common software every connection matters. products, and software compatible with the architecture. The P1024 dual-core processor P1011/P1020 and P2010/P2020 offering a six- supports both symmetric and asymmetric QorIQ P1015 and P1024 chip range of cost-effective solutions. Scaling processing, enabling you to further optimize Communications Processors from a single core at 400 MHz (P1015) to a your design with the same applications running The QorIQ P1 family, which includes the P1015 dual core at 1.2 GHz per core (P2020), on each core or serialize your application using and P1024 communications processors, offers the cores for different processing tasks. the value of smart integration and efficient power for a wide variety of applications in the QorIQ P1015 and P1024 Block DiagramQorIQ P1015 and P1024 Block Diagram networking, telecom, defense and industrial Not on P1015 markets. Based on 45 nm technology for low Security DDR3 SDRAM Power Architecture Power Architecture power, the P1015 and P1024 processors Acceleration Controller e500 Core e500 Core 256 KB provide single- and dual-core options from L2 Cache XOR 32 KB 32 KB 32 KB 32 KB 2 DUART, 2x I C, Timers, 400 MHz to 667 MHz, together with advanced L1 I Cache L1 D Cache L1 I Cache L1 D Cache Interrupt Control, SD/MMC, SPI, security and a rich set of interfaces. 2x USB 2.0/ULPI Coherency Module Enhanced Local Bus System Bus Controller (eLBC) 3x On-Chip NetworkOn-Chip Network TDM Gigabit Ethernet 2x PCI Express 4-ch. DMA Controller4-ch. DMA Controller 4-lane SerDes Core Complex (CPU, L2 and Frontside CoreNet Platform Cache) Basic Peripherals and Interconnect Accelerators and Memory Control Networking ElementsThe P1015 and P1024 processors have an A multi-service router or business gateway Four SerDes to 3.125 GHz multiplexed advanced set of features for ease of use. requires a combination of high performance across controllers The 256 KB L2 cache offers incremental and a rich set of peripherals to support Two PCI Express controllers configuration to partition the cache between the data path throughputs and required Two SGMII interfaces the two cores or to configure it as SRAM or system functionality. The P1015 and P1024 stashing memory. The integrated security devices offer a scalable platform to develop Two high-speed USB controllers (USB 2.0) engine supports the cryptographic algorithms a range of products that can support the Host and device support commonly used in IPsec, SSL, 3GPP and same feature set. Integrated 10/100/1000 other networking and wireless security Ethernet controllers with classification and Enhanced host controller interface (EHCI) QoS capabilities are ideal for managing the protocols. The memory controller offers future- ULPI interface to PHY data path traffic between the LAN and WAN proofing against memory technology migration Enhanced secure digital host interface. PCI Express ports can provide with support for DDR3. It also supports error controller (eSDHC) connectivity to IEEE 802.11n radio cards correction codes, a baseline requirement for for wireless support, TDM for legacy phone any high-reliability system. Serial peripheral interface interfaces to support voice, the USB or SD/ The P1015 and P1024 processors integrate a Integrated security engine (SEC 3.3) MMC interfaces can be used to support local rich set of interfaces, including a multi-protocol storage, the second USB interface is also Crypto algorithm support includes 3DES, SerDes, Gigabit Ethernet, PCI Express and available to support USB attached printers AES, RSA/ECC, MD5/SHA, ARC4, Snow USB. The three 10/100/1000 Ethernet ports or as a console port. And the integrated 3G, and FIPS deterministic RNG support advanced packet parsing, flow control security engine can provide encrypted secure and quality of service features, as well as IEEE Single pass encryption/message communications for remote users with 1588 time-stampingall ideal for managing authentication for common security VPN support. the data path traffic between the LAN and protocols (IPsec, SSL, SRTP, WiMAX) WAN interface. A TDM interface can support Technical Specifications XOR acceleration voice for legacy phone applications. Four Dual (P1024) or single (P1015) high- SerDes lanes can be portioned across two PCI 32-bit DDR3 SDRAM memory controller performance Power Architecture Express ports and two SGMII ports. The PCI with ECC support e500 cores Express ports can provide connectivity to IEEE Programmable interrupt controller (PIC) 802.11n radio cards for wireless support. USB 36-bit physical addressing compliant with OpenPIC standard or SD/MMC interfaces can be used to support Double-precision floating-point support Four-channel DMA controller local storage. A second USB interface is also 32 KB L1 instruction cache and 32 KB L1 available to support USB attached printers or 2 Two I C controllers, DUART, timers data cache for each core as a console port. Multiple memory connection Enhanced local bus controller (eLBC) ports are available, including the 16-bit local 400 MHz to 667 MHz core clock frequency bus, two USB 2.0 controllers, eSDHC and SPI. 16 general-purpose I/O signals 256 KB L2 cache with ECC, also Package: 561-pin wirebond power-BGA configurable as SRAM and Target Applications (TEPBGA1) stashing memory The P1015 and P1024 processors serve in a wide variety of applications. The devices Three 10/100/1000 Mb/s enhanced three- are well-suited for various combinations of speed Ethernet controllers (eTSECs) data plane and control plane workloads in TCP/IP acceleration and networking and telecom applications. With an classification capabilities available junction temperature range of 40 C IEEE 1588 support to +125 C, the devices can be used in power- sensitive defense and industrial applications, Lossless flow control and outdoor environments less protected RGMII, SGMII from the environment. The devices primary target applications are networking and High-speed interfaces (not all telecom linecards. available simultaneously) For more information, please visit freescale.com/QorIQ Freescale, the Freescale logo, PowerQUICC and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. QUICC Engine is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 2010, 2013 Freescale Semiconductor, Inc. Document Number: QP1024FS REV 2