Freescale Semiconductor Document Number: P1021EC Data Sheet: Technical Data Rev. 1, 03/2012 P1021 P1021 QorIQ Integrated Processor Hardware Specifications One four-channel DMA controller The following list provides an overview of the feature set: 2 Two I C controllers, DUART, timers Dual high-performance 32-bit cores, built on Power Enhanced local bus controller (eLBC) Architecture technology: QUICC Engine block 36-bit physical addressing Operating junction temperature (T ) range: 0125C and Double-precision floating-point support j 40C to 125C (industrial specification) 32 Kbyte L1 instruction cache and 32 Kbyte L1 data 31 31 mm 689-pin WB-TePBGA II (wire bond cache for each core temperature-enhanced plastic BGA) 533 MHz to 800 MHz clock frequency 256 Kbyte L2 cache with ECC. Also configurable as SRAM and stashing memory. Three 10/100/1000 Mbps enhanced three-speed Ethernet controllers (eTSECs) TCP/IP acceleration, quality of service, and classification capabilities IEEE 1588 support Lossless flow control MII, RMII, RGMII, SGMII High-speed interfaces supporting various multiplexing options: Four SerDes upto 2.5 GHz/lane multiplexed across controllers Two PCI Express interfaces Two SGMII interfaces High-Speed USB controller (USB 2.0) Host and device support Enhanced host controller interface (EHCI) ULPI interface to PHY Enhanced secure digital host controller (SD/MMC) Enhanced Serial peripheral interface (eSPI) Integrated security engine Protocol support includes ARC4, 3DES, AES, RSA/ECC, RNG, single-pass SSL/TLS XOR acceleration 32-bit DDR2/DDR3 SDRAM memory controller with ECC support Programmable interrupt controller (PIC) compliant with OpenPIC standard 2012 Freescale Semiconductor, Inc. All rights reserved.Table of Contents 1 Pin Assignments and Reset States 4 2.16 JTAG 82 1.1 Ball Layout Diagrams .4 2.17 I2C 84 1.2 Pinout Assignments 9 2.18 High-Speed Serial Interfaces (HSSI) 86 2 Electrical Characteristics 32 2.19 PCI Express . 92 2.1 Overall DC Electrical Characteristics 32 3 QUICC Engine Block Specifications . 97 2.2 Power Sequencing 36 3.1 Ethernet Interface 97 2.3 Power Down Requirements .37 3.2 HDLC, BISYNC, Transparent, and Synchronous UART 2.4 RESET Initialization .37 Interfaces 100 2.5 Power-on Ramp Rate 38 3.3 TDM/SI . 103 2.6 Power Characteristics 38 3.4 UTOPIA Interface . 104 2.7 Input Clocks .40 3.5 SPI Interface . 106 2.8 DDR2 and DDR3 SDRAM 44 3.6 GPIO . 108 2.9 eSPI .53 4 Thermal 109 2.10 DUART .55 4.1 Thermal Characteristics . 109 2.11 Ethernet: Enhanced Three-Speed Ethernet (eTSEC) 4.2 Temperature Diode 110 (10/100/1000Mbps)MII/RMII/RGMII/SGMII Electrical 5 Package Information 110 Characteristics .56 5.1 Package Parameters for the P1021 WB-TePBGA II . 110 2.12 USB 72 5.2 Ordering Information . 113 2.13 Enhanced Local Bus .75 6 Product Documentation 113 2.14 Enhanced Secure Digital Host Controller (eSDHC) .79 7 Revision History . 114 2.15 Programmable Interrupt Controller (PIC) Specifications81 P1021 QorIQ Integrated Processor Hardware Specifications, Rev. 1 2 Freescale Semiconductor