Freescale Semiconductor Document Number: AN2490/D Application Note Rev. 1, 09/2009 e300 (MPC603e) and e500 Register Model Comparison Contents The products described in this document are microprocessor 1 Migrating from PowerPC AIM Architecture to Power cores built on Power Architecture technology. This ISA Register Model 2 application note outlines the differences between the 2 Special-Purpose Registers by SPR Number 4 3 Special-Purpose Registers by SPR Abbreviation . 13 registers implemented in the e300 core (MPC603e 4 Architecture-Defined Non-SPR Registers by processor) and the e500 microprocessor core. It also Abbreviation 20 discusses the differences between the register models 5 Freescale EIS-Defined Performance Monitor Registers (PMRs) 20 defined by the Apple/IBM/Motorola (AIM) version and 6 Revision History 23 those defined by the Power instruction set architecture (Power ISA). Registers defined by both the AIM version of the PowerPC architecture and Power ISA are identified by the level of the architecture at which the register is defined, as follows: Book I, user instruction set architecture (UISA) Book II, virtual environment architecture (VEA) Book III or III-E (Book III for AIM, Book III-E for Power ISA), operating environment architecture (OEA) Book IV, implementation definition In addition, Power ISA also includes a fourth book, called Book VLE, which contains additional definitions. Neither the e300 or the e500 cores contain registers defined by Book VLE. Freescale Semiconductor, Inc., 2009. All rights reserved. Migrating from PowerPC AIM Architecture to Power ISA Register Model For Power ISA, some registers defined in Book I and Book II may have slightly different definitions based on the category in which they are classified. Readers should generally use the definition given for the Embedded category if such a distinction exists. Registers identified as EIS are defined as part of the Freescale extensions to Power ISA by the EREF. Although some of these registers may also be defined in Power ISA, if identified as EIS, these registers contain additional fields and or semantics that are not defined in Power ISA. NOTE This document does not attempt to identify specific differences between register fields implemented in a register. For example, although most machine state register (MSR) fields are the same in all processors, each device typically has implementation-specific fields that are not identified in this document. Consult the users manuals for full descriptions of register fields. 1 Migrating from PowerPC AIM Architecture to Power ISA Register Model Migrating from the PowerPC AIM register model implemented in the 603e to the Power ISA register model implemented in the e500 is relatively straightforward, keeping in mind the following points: Bit numbering in Power ISA registers has changed so that bits in 32-bit registers use a 64-bit numbering scheme in which the lower 32 bits are numbered 3263, but correspond exactly to bits 031 in the 32-bit AIM definition of the PowerPC architecture as implemented in the e300. User-level software is binary upw ardly compatible across both versions of the architecture, so most of the changes appear in registers that are defined by Book III-E and Book II, primarily associated with the memory-management unit (MMU), timer, and interrupt register models. Note that e500v1 and e500v2 cores do not implement Power ISA category Floating Point, but do support the Embedded floating point subcategories defined under category SPE. This means that user-level software that employs floating point from e300 is not binary compatible with e500v1 and e500v2 cores and will generally require software to be recompiled. e500mc cores implement Power ISA category Floating Point and do not require user-level software to be recompiled. The MMU register model differences are as follows: The Power ISA does not support the following 32-bit MMU-related registers: Instruction and data block address translation registers (IBATs and DBATs). Segment registers (SR0SR15) The Power ISA defines a new process identification register (PID) The EIS defines the following additional MMU registers: Process ID registers (PID1PID2) for e500v1 and e500v2. Note that the EIS defines the Power ISA PID register as PID0. MMU control and status register 0 (MMUCSR0) MMU configuration register (MMUCFG) e300 (MPC603e) and e500 Register Model Comparison, Rev. 1 2 Freescale Semiconductor