P1022NSE2LFB NXP

Freescale Semiconductor Document Number: P1022EC Data Sheet: Technical Data Rev. 2, 9/2013 P1022 P1022 QorIQ Integrated Processor Hardware WB-TePBGA II689 31 mm x 31 mm Specifications The following list provides an overview of the P1022 feature TCP/IP acceleration, quality of service, and set: classification capabilities IEEE Std 1588 support Two high-performance 32-bit e500v2 cores that implement Lossless flow control the Power Architecture technology: RGMII, RMII, SGMII 36-bit physical addressing Two four-channel DMA controllers Double-precision floating-point support 87 general-purpose I/O signals 32 KB L1 instruction cache and 32 KB L1 data cache for Three PCI Express controllers each core Dual serial ATA (SATA) controllers 400-MHz to 1067-MHz clock frequency TDM Interface 256 KB L2 cache with ECC. Also configurable as SRAM Power management and stashing memory. System performance monitor e500 coherency module (ECM) manages core and System access port intrasystem transactions IEEE Std 1149.1- compatible, JTAG boundary scan Integrated security engine (SEC) 31 31 mm 689-pin WB-TePBGA II (wire bond Protocol support includes ARC4, 3DES, AES, temperature-enhanced plastic BGA) RSA/ECC, RNG, single-pass SSL/TLS XOR acceleration 64-bit DDR2/DDR3 SDRAM memory controller with ECC support 32/64 bit data interface DDR2/3 supported for data rate up to 800 MT/s Four banks of memory supported, each up to 8 GB Programmable interrupt controller (PIC) compliant with OpenPIC standard 2 Dual I C controllers Enhanced secure digital host controller (SD/MMC) Enhanced Serial peripheral interface (eSPI) Enhanced local bus controller (eLBC) Display interface unit (DIU) I2S interface supported through synchronous serial interface (SSI) DUART Two High-Speed USB controller (USB 2.0) Host and device support Enhanced host controller interface (EHCI) ULPI interface to PHY Two enhanced three-speed Ethernet controllers (eTSECs) 2011-2013 Freescale Semiconductor, Inc. All rights reserved.Table of Contents 1 Pin assignments and reset states .4 2.15 Display interface unit 63 1.1 Ball layout diagrams 4 2.16 Synchronous Serial Interface (SSI) . 66 1.2 Pinout assignments .9 2.17 Programmable Interrupt Controller (PIC) specifications69 2 2 Electrical characteristics .23 2.18 I C 69 2.1 Overall DC electrical characteristics .23 2.19 GPIO 71 2.2 Power sequencing .26 2.20 TDM . 73 2.3 Power down requirements .27 2.21 High-Speed Serial Interfaces (HSSI) 75 2.4 RESET initialization .27 2.22 PCI express . 81 2.5 Power-on ramp rate 28 2.23 Serial ATA (SATA) 84 2.6 Power characteristics 28 2.24 JTAG controller 88 2.7 Input clocks 31 3 Thermal . 90 2.8 DDR2 and DDR3 SDRAM controller .33 3.1 Thermal characteristics 90 2.9 eSPI .40 4 Package information . 92 2.10 DUART .42 4.1 Package parameters for the P1022WB-TePBGA II . 92 2.11 Ethernet: Enhanced Three-Speed Ethernet (eTSEC), 4.2 Ordering information 93 MII management 43 4.3 Part marking 93 2.12 USB 55 5 Product documentation . 94 2.13 Enhanced local bus interface 57 6 Revision History 94 2.14 Enhanced secure digital host controller (eSDHC) 61 P1022 QorIQ Integrated Processor Hardware Specifications, Rev. 2 2 Freescale Semiconductor