QorIQ Multicore Processor Development P1 Series P1023 and P1017 high-performance QorIQ communications processors The QorIQ P1023 processor integrates a rich Freescale QorIQ communications platforms The P1023 processor includes a performance- set of interfaces including SerDes, Gigabit are the next-generation evolution of our optimized implementation of the QorIQ Data Ethernet, three PCI Express leading PowerQUICC communications Path Acceleration Architecture (DPAA). This controller and processors. Built using high-performance architecture provides the infrastructure to USB. The two 10/100/1000 Ethernet ports Power Architecture cores, QorIQ platforms support simplified sharing of networking support advanced packet parsing, flow control enable a new era of networking innovation interfaces and accelerators by multiple and quality of service features, as well as IEEE where the reliability, security and quality of CPU cores. The DPAA significantly reduces 1588 time-stampingall ideal for managing the service for every connection matters. software overhead associated with high touch data path traffic between the LAN and WAN packet forwarding operations. Examples of interface. Four SerDes lanes can be portioned QorIQ P1023 and P1017 the types of packet processing services this across three PCI Express ports and two SGMII Communications Processors architecture is optimized to support include ports. The PCI Express ports can provide traditional routing and bridging, firewall, connectivity to IEEE 802.11n and 802.11ac The P1023 and P1017 processors offer the VPN termination for IPSec and MACSec (a radio cards for wireless support. USB or SD/ value of extensive integration including a high- standardized form of Ethernet encapsulation MMC interfaces can be used to support local performance data path which can off-load that can be used to provide confidentiality). storage. specific protocol processing from the CPUs. The P1023 and P1017 are ideally suited for The 256 KB L2 cache offers incremental Target Applications high-performance enterprise WLAN, fixed configuration to partition the cache between The P1023 and P1017 processors serve routers and security gateway applications. the two cores or to configure it as SRAM or a wide variety of applications. The devices The P1023 device supports 500 MHz in dual stashing memory. The integrated security are well-suited for various combinations of core mode or 800 MHz in single core mode, features include support for data integrity data plane and control plane workloads in along with advanced security and a rich set of and authenticity protection over Ethernet, networking and telecom applications. With interfacesall delivered on 45 nm technology as well as a security engine which supports an available junction temperature range of for low power implementation. cryptographic algorithms commonly used in -40C to +105C, the devices can be used IPsec, SSL, 3GPP and other networking and in power-sensitive defense and industrial wireless security protocols. It also provides applications, as well as outdoor environments header and trailer offload for security protocols less protected from the environment. The such as IPSec, SSL/TLS, SRTP 802.1ae, devices primarily target applications such as 802.11i and 802.16e. The memory controller networking and telecom linecards. offers future-proofing against memory technology migration with support for DDR3/ DDR3L. A wireless router or business gateway requires QorIQ P1023/17 Communication Processors QorIQ P1023/17 Communication Processors a combination of high performance and a rich set of peripherals to support the data path Power Architecture throughputs and required system functionality. e500-v2 Core The P1017 single-core and P1023 dual-core 256 KB 32-bit 32 KB 32 KB devices offer a scalable platform to develop Frontside DDR3/3L D-Cache I-Cache Cache Memory Controller a range of products that can support the USB 2.0 P1017Single Core Only same feature set. Integrated 10/100/1000 eLBC Coherent System Bus Ethernet controllers with data path offload for SD/MMC classification and QoS capabilities are ideal for DUART Frame Manager managing the data path traffic between the 2 2x I C Security Queue DMA LAN and WAN interface. PCI Express ports 4.2 Mgr. SPI, GPIO Parse, Classify, Distribute can provide connectivity to IEEE 802.11n and 802.11ac radio cards for wireless support, PCIe PCIe Buffer PCle Mgr. 1 GE 1 GE the USB or SD/MMC interfaces can be used to support local storage, and the integrated 4-Lane 2.5 GHz SerDes security engine can provide encrypted secure communications for remote users with Core Complex (CPU and L2 Cache) Basic Peripherals and Interconnect VPN support. Accelerators and Memory Control Networking Elements Technical Specifications High-speed interfaces (not all available Serial peripheral interface Single (P1017) and dual (P1023) high- simultaneously) performance Power Architecture e500 32-bit DDR3/DDR3L SDRAM cores Three PCI Express controllers memory controller 36-bit physical addressing Two SGMII interfaces Programmable interrupt controller compliant with OpenPIC standard Double-precision floating-point support Four SerDes to 3.125 GHz multiplexed across controllers Four-channel DMA controller 32 KB L1 instruction cache and 32 KB 2 L1 data cache for each core Integrated security engine (SEC 4.2) Two I C controllers, DUART, timers 400 MHz to 800 MHz core clock Crypto algorithm support includes Enhanced local bus controller frequency 3DES, AES, RSA/ECC, MD5/ 16 general-purpose I/O signals SHA, ARC4, SNOW 3G and FIPS 256 KB L2 cache with ECC, also Package: 457-pin wirebond power-BGA deterministic RNG configurable as SRAM and stashing (TEPBGA1) memory Single pass encryption/message authentication for common security Two 10/100/1000 Mbps three-speed Enablement protocols (IPsec, SSL, SRTP, DTLS) Ethernet controllers Green Hills Software: Complete portfolio XOR acceleration of software and hardware development TCP/IP acceleration and tools, trace tools and real-time operating classification capabilities High-Speed USB controllers (USB 2.0) systems IEEE 1588 support Host and device support Mentor Graphics : Commercial grade Lossless flow control Enhanced host controller interface Linux solution RGMII, SGMII ULPI interface to PHY CodeSourcery: GCC and GDB tool chain MACSec (IEEE 802.1ae) encapsulation Enhanced secure digital host controller Development system and decapsulation For more information, visit freescale.com/QorIQ Freescale, the Freescale logo, PowerQUICC and QorIQ are trademarks of FreescaleSemiconductor,Inc., Reg. U.S. Pat. & Tm. Off. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. All other product or service names are the property of their respective owners. 2012FreescaleSemiconductor,Inc. Document Number: QORIQP1023FS REV 1