74ABT125BQ,115 Nexperia

74ABT125 Quad buffer 3-state Rev. 8 30 June 2021 Product data sheet 1. General description The 74ABT125 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. This device is fully specified for partial power down applications using I . The I circuitry disables OFF OFF the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits Supply voltage range from 4.5 V to 5.5 V BiCMOS high speed and output drive Direct interface with TTL levels Power-up 3-state Inputs are disabled during 3-state mode I circuitry provides partial Power-down mode operation OFF Latch-up protection exceeds 500 mA per JESD78B class II level A Quad bus interface 3-state buffers Live insertion and extraction permitted Output capability: HIGH -32 mA LOW +64 mA ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 C to +85 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ABT125D -40 C to +85 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74ABT125PW -40 C to +85 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74ABT125BQ -40 C to +85 C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package no leads 14 terminals body 2.5 3 0.85 mmNexperia 74ABT125 Quad buffer 3-state 4. Functional diagram 2 1A 1Y 3 2 1 1 1OE 3 1 EN1 5 2A 2Y 6 5 4 2OE 6 4 9 3A 3Y 8 9 8 3OE 10 10 4A 4Y nA nY 12 11 12 11 4OE 13 13 nOE mna228 mna229 mna227 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one buffer) 5. Pinning information 5.1. Pinning 74ABT125 terminal 1 index area 1A 2 13 4OE 1Y 3 12 4A 74ABT125 2OE 4 11 4Y 2A 5 (1) 10 3OE GND 1OE 1 14 V CC 2Y 6 9 3A 1A 2 13 4OE 1Y 3 12 4A 2OE 4 11 4Y 001aai028 2A 5 10 3OE Transparent top view 2Y 6 9 3A (1) This is not a ground pin. There is no electrical or GND 7 8 3Y mechanical requirement to solder the pad. In case 001aai027 soldered, the solder land should remain floating or connected to GND. Fig. 4. Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1OE, 2OE, 3OE, 4OE 1, 4, 10, 13 output enable input (active LOW) 1A, 2A, 3A, 4A 2, 5, 9, 12 data input 1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) V 14 supply voltage CC 74ABT125 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 8 30 June 2021 2 / 12 GND 7 1 1OE 3Y 8 14 V CC