QorIQ Communications Platforms
QorIQ P2040 and
P2041 Processors
Overview
The QorIQ P2040 (up to 1.2 GHz) and higher Virtualization
DPAA
performance pin-compatible P2041
The QorIQ P2 family includes support for
Data Path Acceleration Architecture is a set
(up to 1.5 GHz) quad-core processors, built on
hardware-assisted virtualization. The 500mc
of blocks that, together, offloads basic work
Power Architecture technology, bring high-
core supports a hardware hypervisor that is
from the cores, allowing the cores to perform
end architectural features pioneered in the P4
designed to enable each core to run its own
higher value tasks or to achieve application
family into the mid-performance P2040 and
operating system completely independent
performance targets at lower frequency, cost
P2041 quad-core devices. This helps to enable
of the other core. The hypervisor facilitates
and power. The DPAA consists of:
customers to scale software up and down the
resource sharing and partitioning in a multicore
Frame manager, which implements policing,
QorIQ portfolio.
environment and provides protection in the
classification and scheduling over
event that a core, driven by malicious or
The architectural commonalities with other
Ethernet ports
improperly programmed code, tries to access
QorIQ products include the e500mc core,
Queue manager, which performs queuing,
memory does not have permission to read or
hardware hypervisor for robust virtualization
congestion control and workload
write. It also allows the sharing and partitioning
support, Data Path Acceleration Architecture
distribution and packet ordering
of various I/Os across the cores and helps
(DPAA) for offloading packet handling tasks
ensure that incoming memory mapped
from the core, and the CoreNet switch fabric
Buffer manager, which assigns packets
transactions are written only into appropriate
which eliminates internal bottlenecks.
to right-sized buffers to minimize
ranges of the memory map.
memory consumption
The architectural similarities are complemented
by a DPAA application programming interface
(API) such that all devices with DPAA are
QorIQ P2 Family Comparison Chart
programmed in the same manner. Additionally,
P2040 P2041
all DPAA devices are supported with common
Frequency range 6671200 MHz 12001500 MHz
GUI-based configuration tools and use case
Cache hierarchy 32 KB I/D + 1 MB 32 KB I/D + 128 KB
CoreNet platform cache L2/core + 1 MB CoreNet platform cache
applications, which are simple applications
Ethernet connectivity 5x Gigabit Ethernet 5x Gigabit Ethernet + XAUI (10 GE)
that establish the basic infrastructure of
programming the DPAA. Developers can build
applications on top of these. With these tools,
code written for other DPAA-enabled devices
QorIQ P2040/P2041 Processors Block Diagram
QorIQ P2040/P2041 Communication Processors
can easily be developed and ported to the
P2040 processor.
Power Architecture
e500mc Core
128 KB
Backside
The P2040 and P2041 processors are pin
L2 Cache 1024 KB 64-bit
32 KB 32 KB
Frontside CoreNet DDR3/3L
(P2041 only)
compatible, sharing a 23 x 23 mm package. D Cache I Cache
Platform Cache Memory Controller
The P2041 is a superset of the P2040. The
Security Fuse Processor
CoreNet Coherency Fabric
Security Monitor
unique characteristics of each device are
PAMU PAMU PAMU PAMU
2x USB 2.0 with PHY
outlined to the right.
eSDHC
Frame Manager Real-Time Debug
Serial
Queue
16-bit eLBC Security
Watchpoint
RapidIO
DMA DMA
Mgr.
4.2 Parse, Classify, Cross
Additional features supported by both devices SD/MMC Mgr.
Trigger
Distribute SATA SATA
2x DUART
2.0 2.0
include up the three PCI Express ports, two Perf. CoreNet
Pattern
2 1GE 1GE
Monitor Trace
4x I C
10GE
Match Buffer PCIe SRIO SRIO
PCIe
1GE
(P2041
Serial RapidIO ports, two SATA ports and two Engine Mgr. PCIe
SPI, GPIO
Aurora
only)
1GE 1GE
2.1
USB interfaces.
10-Lane 5 GHz SerDes
Core Complex (CPU, L2 and Frontside CoreNet Platform Cache) Basic Peripherals and Interconnect
Accelerators and Memory Control Networking Elements Security block for implementing
QorIQ P2040/P2041 Features List
crypto algorithms
Four e500mc cores, built on 4x e500mc cores (P2040: up to 1.2 GHz; P2041: up to 1.5 GHz)
Power Architecture technology
RapidIO message manager, which allows
32 KB L1-I cache and 32 KB L1-D cache per core
128 KB L2 cache per core (P2041 only)
Type9 and Type11 packets to connect
Memory controller DDR3/3L up to 1.2 GHz (P2040) and 1.33 GHz (P2041)
directly with DPAA infrastructure
32/64-bit data bus w/ECC
Pattern matching engine to search for
High-Speed interconnects 10 x 5 GHz SerDes lanes
text strings in packets for unified threat
3 x PCI Express 2.0 controllers
2 x Serial RapidIO 1.3/2.1 controllers
management
2 x SATA 2.0 at 3 GB/s
The DPAA achieves near-linear scaling as
CoreNet switch fabric 1 MB CoreNet platform cache with ECC
additional cores are applied to a task.
Peripheral access management unit (PAMU) controls external device
access to memory space
Ethernet One 10-Gigabit Ethernet (XAUI) controller (P2041 only)
CoreNet Switch Fabric
Up to 5x SGMII, 4x 2.5 GB/s SGMII, 2x RGMII
The fabric-based interface provides scalable
All with classification, hardware queueing, policing, buffer management,
checksum offload, QoS, lossless flow control, IEEE 1588
on-chip, point-to-point connectivity supporting
concurrent traffic to and from multiple Data path acceleration SEC 4.2: Public key accelerator, DES, AES, message digest accelerator,
random number generator, ARC4, SNOW 3G F8 and F9, CRC, Kasumi
resources connected to the fabric, eliminating
PME 2.1: Searches for 128 byte text strings in 32 KB patterns in 128
single-point bottlenecks for non-competing million sessions
RapidIO messaging: Type 9 and 11
resources. This is designed to eliminate bus
Additional peripheral interfaces SD/MMC
contention and latency issues associated
SPI controller
with scaling shared bus architectures that are
2
Four I C controllers
common in other multicore approaches.
2x USB 2.0 with PHY
Two dual UARTs
Enhanced local bus controller (eLBC), 16-bit
Secure Boot
Device 45 nm SOI process technology
The secure boot feature ensures that the
783-pin FCPBGA package, 23 x 23 mm
P2040 and P2041 processors only run
authenticated code. Through a set of fuses
Software and Tools Support
With over a 2x performance range in a single
that OEMs can program once but can never
package, the P2040 and P2041 processors
Enea : Real-time operating system support
be read, secure boot prevents unauthorized
together allow customers to use bill of
parties from reverse engineering code to steal
Green Hills : Complete portfolio of software
materials stuffing options in a single board
intellectual property, from loading illegitimate
and hardware development tools, trace
to develop a range of products at different
code to change system functionality or from
tools and real-time operating systems
performance and price points. For instance, the
extracting sensitive user information that may
Mentor Graphics : Commercial-grade
P2040 processor addresses the fixed router
be stored in the system.
Linux solution
and the P2041 processor the modular router.
The P2040 may address the LTE channel
Target Applications CodeSourcery: GCC and GDB tool chain
card while the P2041 addresses the network
The P2040 and P2041 processors are
P2040 and P2041 reference design
interface card. Other applications include UTM,
targeted at mixed control plane and data plane
board (RDB)
aerospace and defense, multi-function printers
applications, where in previous generations,
and factory automation.
separate devices would implement each
function. Typically, one or two cores would
implement the control plane, while the
remaining cores implement the data plane.
The hardware hypervisor facilitates this, with
its capability to safely provision flexible core
allocations into groups running SMP, one
core running alone, separate cores running in
parallel or a core running end-user applications.
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Document Number: QP2040FS REV 3