Freescale Semiconductor Document Number: P2041EC Data Sheet: Technical Data Rev. 2, 02/2013 P2041 P2041 QorIQ Integrated Processor FCPBGA780 23 mm x 23 mm Hardware Specifications The P2041 QorIQ integrated communication processor Three PCI Express 2.0 controllers/ports combines four Power Architecture processor cores with Two serial RapidIO controllers/ports (sRIO port) high performance data path acceleration logic and network supporting version 1.3 with features 2.1 and peripheral bus interfaces required for networking, Two serial ATA (SATA 2.0) controllers telecom/datacom, wireless infrastructure, and aerospace Enhanced secure digital host controller (SD/MMC) applications. Enhanced serial peripheral interface (eSPI) 2 high-speed USB 2.0 controllers with integrated PHYs This chip can be used for combined control, data path, and application layer processing in routers, switches, base station controllers, and general-purpose embedded computing. Its high level of integration offers significant performance benefits compared to multiple discrete devices, while also greatly simplifying board design. This chip includes the following functions and features: Four e500mc Power Architecture cores, each with a backside 128 KB L2 Cache with ECC Three levels of instructions: User, supervisor, and hypervisor Independent boot and reset Secure boot capability CoreNet fabric supporting coherent and non-coherent transactions amongst CoreNet endpoints One 1 MB CoreNet platform cache with ECC CoreNet bridges between the CoreNet fabric the I/Os, data path accelerators, and high and low speed peripheral interfaces One 10-Gigabit Ethernet (XAUI) controller Five 1-Gigabit Ethernet controllers 2.5 Gbps SGMII interfaces RGMII interfaces One 64-bit DDR3 and DDR3L SDRAM memory controller with ECC Multicore programmable interrupt controller 2 Four I C controllers Four 2-pin UARTs or two 4-pin UARTs Two 4-channel DMA engines Enhanced local bus controller (eLBC) 20102013 Freescale Semiconductor, Inc. All rights reserved.Table of Contents 2 1 Pin Assignments and Reset States .3 2.18 I C 80 1.1 780 FC-PBGA Ball Layout Diagrams .4 2.19 GPIO 83 1.2 Pinout List 9 2.20 High-Speed Serial Interfaces (HSSI) 84 2 Electrical Characteristics 37 3 Hardware Design Considerations 114 2.1 Overall DC Electrical Characteristics 37 3.1 System Clocking 114 2.2 Power Up Sequencing .42 3.2 Supply Power Default Setting 121 2.3 Power Down Requirements 44 3.3 Power Supply Design 123 2.4 Power Characteristics 45 3.4 Decoupling Recommendations . 125 2.5 Thermal .48 3.5 SerDes Block Power Supply Decoupling 2.6 Input Clocks .48 Recommendations . 125 2.7 RESET Initialization .51 3.6 Connection Recommendations . 125 2.8 Power-on Ramp Rate 52 3.7 Recommended Thermal Model . 134 2.9 DDR3 and DDR3L SDRAM Controller .52 3.8 Thermal Management Information 134 2.10 eSPI .59 4 Package Information 136 2.11 DUART .61 4.1 Package Parameters for the FC-PBGA . 136 2.12 Ethernet: Data path Three-Speed Ethernet (dTSEC), 4.2 Mechanical Dimensions of the FC-PBGA . 137 Management Interface, IEEE Std 1588 .62 5 Security Fuse Processor . 138 2.13 USB 70 6 Ordering Information 138 2.14 Enhanced Local Bus Interface .71 6.1 Part Numbering Nomenclature . 138 2.15 Enhanced Secure Digital Host Controller (eSDHC) .75 6.2 Orderable Part Numbers Addressed by this Document138 2.16 Multicore Programmable Interrupt Controller (MPIC) 7 Revision History . 140 Specifications 77 2.17 JTAG Controller .78 P2041 QorIQ Integrated Processor Hardware Specifications, Rev. 2 2 Freescale Semiconductor