QorIQ Communications Platforms P Series QorIQ P5020 and P5010 communications processors Overview e5500 Core DPAA Hardware Accelerators The QorIQ P5 family delivers scalable 64-bit The P5020 is based on the 64-bit e5500 Frame manager (FMAN) 12 Gb/s classify, parse processing with single-, dual- and quad-core Power Architecture core. The e5500 and distribute Buffer manager (BMAN) 64 buffer pools devices. With frequencies scaling up to core uses a seven-stage pipeline for low 24 Queue manager (QMAN) Up to 2 queues 2.0 GHz, a tightly coupled cache hierarchy latency response to unpredictable code Security (SEC) 17 Gb/s: 3 DES, AES for low latency and integrated hardware execution paths, boosting its single-threaded Pattern matching engine 10 Gb/s aggregate acceleration, the P5020 (dual-core) and performance. Key features: (PME) P5010 (single-core) devices are ideally suited Supports up to 2 GHz core frequencies RapidIO manager Supports Type 9 and for compute intensive, power-conscious Type 11 messaging Tightly coupled low latency cache control plane applications. RAID5/6 engine Calculates parity for network attached hierarchy: 32 KB I/D (L1), 512 KB L2 storage and direct per core Target Markets attached storage applications and Applications Up to 2 MB of shared platform cache (L3) The P5020 is designed for high-performance, 3 DMIPS/MHz per core Data Path Acceleration power-constrained control plane applications Architecture (DPAA) Up to 64 GB of addressable memory space and provides an ideal combination of core The P5020 integrates QorIQ DPAA, an performance, integrated accelerators and Hybrid 32-bit mode to support legacy innovative multicore infrastructure for advanced I/O required for the following software and seamless transition to 64-bit scheduling work to cores (physical and virtual), compute-intensive applications: architecture hardware accelerators and network interfaces. Enterprise equipment: Router, switch, The FMAN, a primary element of the DPAA, Virtualization services parses headers from incoming packets and The P5020 includes support for hardware- Data center: Server appliance, SAN classifies and selects data buffers with optional assisted virtualization. The e5500 core offers storage controller, iSCSI controller, policing and congestion management. The an extra core privilege level (hypervisor). FCoE bridging FMAN passes its work to the QMAN, which Virtualization software for the P5 family assigns it to cores or accelerators with a multi- Aerospace and defense includes kernel-based virtual machine (KVM), level scheduling hierarchy. The P5020 also Linux containers, Freescale hypervisor and Industrial computing: Single-board offers accelerators for cryptography, enhanced commercial virtualization software from Green computers, test/measurement, robotics regular expression pattern matching and Hills Software and Enea . RAID5/6 offload. QorIQ P5020/P5010 Processors Block Diagram QorIQ P5020/P5010 Processors *Only Available on P5020 *Only Available on P5020 1024 KB 64-bit Power Architecture Frontside CoreNet DDR2/3 512 KB e5500 Core Platform Cache Memory Controller Backside 1024 KB 64-bit L2 Cache 32 KB 32 KB Frontside CoreNet DDR2/3 D Cache I Cache Platform Cache Memory Controller Security Fuse Processor CoreNet Coherency Fabric 2x Full Speed USB w/PHY Peripheral Access PAMU PAMU PAMU PAMU eSDHC Management Unit eLBC Frame Manager Real-Time Debug Serial RapidIO SD/MMC Security Queue Watchpoint RapidIO Message 2x DMA Mgr. 4.0 Parse, Classify, Cross 2x DUART Mgr. Unit Trigger Distribute SATA SATA 2 2x I C 2.0 2.0 Perf. Pattern 1GE 1GE Trace RAID PCIe/ SPI, GPIO Monitor Match Buffer PCIe PCIe SRIO 5/6 10 GE 1GE SRIO Engine Mgr. PCIe Engine Aurora 1GE 1GE 2.0 18-Lane 5 GHz SerDes Core Complex (CPU, L2 and Frontside CoreNet Platform Cache) Basic Peripherals and Interconnect Accelerators and Memory Control Networking Elements P5 Family Comparison Chart P5020/P5010 P5040/P5021 CPU cores 2x 64-bit e5500, 1x (P5010) 4x 64-bit e5500, 2x (P5021) Threads 2/1 (single thread per core) 4/2 (single thread per core) Max core frequency 1.6 to 2 GHz 1.8 to 2.2 GHz L2 512 KB per core 512 KB per core L3/Platform 2 MB (P5020)/1 MB (P5010) 2 MB (both P5040 and P5021) DDR I/F 2x 64-bit DDR3 (up to 1333 MT/s) 2x 64-bit DDR3 (up to 1600 MT/s) 1x 64-bit DDR3 (P5010) PCI Express 4x PCIe v2.0 3x PCIe v2.0 (incl. 1 x 8) GbE, 10 GbE 5x 1 GbE, 1x 10 GbE 10x 1 GbE, 2x 10 GbE SRIO 2x SRIO v2.1 (supports Type 9 and 11 messaging) N/A SerDes lanes 18 lanes 20 lanes Package 1295-pin 37.5 x 37.5 mm FC-PBGA 1295-pin 37.5 x 37.5 mm FC-PBGA System Peripherals and P5020/P5010 Features List Networking Two (P5020) or one (P5010) Up to 2 GHz with 64-bit ISA support (Power Architecture V2.06 compliant) single threaded e5500 cores For networking, the FMAN supports one Three levels of instruction: User, supervisor, hypervisor built on Power Architecture Hybrid 32-bit mode to support legacy software and transition to 64-bit 10 Gb/s and 5x 1 Gb/s MAC controllers that technology architecture connect to PHYs, switches and backplanes CoreNet platform cache (CPC) 2 MB configured as dual 1 MB blocks (1 MB only for P5010) over RGMII, SGMII and XAUI. High-speed Hierarchical interconnect fabric CoreNet fabric supporting coherent and non-coherent transactions with system expansion is supported through four prioritization and bandwidth allocation amongst CoreNet endpoints PCI Express v2.0 controllers that support QMAN fabric supporting packet-level queue management and quality of service scheduling a variety of lane widths. Other peripherals Two 64-bit DDR3/3L SDRAM Up to 1333 MT/s 2 include SATA, SD/MMC, I C, UART, SPI, NOR/ memory controllers with ECC Memory pre-fetch engine and interleaving support NAND controller, GPIO and dual 1333 MT/s DDR3/3L controllers. DPAA incorporating acceleration Packet parsing, classification and distribution (FMAN) for the following functions QMAN for scheduling, packet sequencing and congestion management Hardware BMAN for buffer allocation and de-allocation Software and Tool Support Cryptography acceleration (SEC 4.2) at up to 40 Gb/s Enea: Real-time operating system support RegEx pattern matching acceleration (PME 2.1) at up to 10 Gb/s and virtualization software SerDes 18 lanes at up to 5 Gb/s Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Green Hills: Comprehensive portfolio of Ethernet interfaces One 10 Gb/s Ethernet MACs software and hardware development tools, 5x 1 Gb/s Ethernet MACs trace tools, real-time operating systems High-speed peripheral interfaces Four PCI Express 2.0 controllers and virtualization software Two Serial RapidIO controllers/ports (sRIO port) V1.3-compliant with features of V2.1 Mentor Graphics : Commercial-grade Two serial ATA (SATA 2.0) controllers Linux solution Additional peripheral interfaces Two USB 2.0 Full-Speed controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) QNX : Real-time OS and development tool Enhanced serial peripheral interface 2 support Four I C controllers Four UARTs QorIQ P5020 development system Integrated flash controller supporting NAND and NOR flash (P5020DS) DMA Dual four channel Support for hardware Extra privileged level for hypervisor support virtualization and partitioning enforcement QorIQ trust architecture 1.1 Secure boot, secure debug, tamper detection, volatile key storage For more information, please visit freescale.com/QorIQ Freescale, the Freescale logo and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm Off. CoreNet is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 2012, 2014 Freescale Semiconductor,Inc. Document Number: QP5020FS REV 6