PCA9515 2 I C-bus repeater Rev. 09 23 April 2009 Product data sheet 1. General description 2 The PCA9515 is a BiCMOS integrated circuit intended for application in I C-bus and SMBus systems. 2 While retaining all the operating modes and features of the I C-bus system, it permits 2 extension of the I C-bus by buffering both the data (SDAn) and the clock (SCLn) lines, thus enabling two buses of 400 pF. 2 The I C-bus capacitance limit of 400 pF restricts the number of devices and bus length. Using the PCA9515 enables the system designer to isolate two halves of a bus, thus more devices or longer length can be accommodated. It can also be used to run two buses, one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the 100 kHz bus is isolated when 400 kHz operation of the other is required. Two or more PCA9515s cannot be put in series. The PCA9515 design does not allow this conguration. Since there is no direction pin, slightly different legal low voltage levels are used to avoid lock-up conditions between the input and the output. A regular low applied at the input of a PCA9515 will be propagated as a buffered low with a slightly higher value. When this buffered low is applied to another PCA9515, PCA9516A, or PCA9518A in series, the second PCA9515, PCA9516A, or PCA9518A will not recognize it as a regular low and will not propagate it as a buffered low again. The PCA9510A/9511A/9513A/9514A and PCA9512A cannot be used in series with the PCA9515, PCA9516A, or PCA9518A but can be used in series with themselves since they use shifting instead of static offsets to avoid lock-up conditions. The PCA9515 SCLn/SDAn C is about 200 pF versus the normal < 10 pF when V =0V. i CC The newer PCA9515A should be used in applications where power is secured to the repeater but an active bus remains on either set of SCLn/SDAn pins to prevent this increase in bus loading. Additionally, the PCA9515A has a wider voltage range of 2.3 V to 3.6 V and can be used in applications with lower voltage supply constraints. 2. Features n 2 channel, bidirectional buffer 2 n I C-bus and SMBus compatible n Active HIGH repeater enable input n Open-drain input/outputs n Lock-up free operation n Supports arbitration and clock stretching across the repeater 2 n Accommodates Standard-mode and Fast-mode I C-bus devices and multiple masters 2 n Powered-off high-impedance I C-bus pins n Operating supply voltage range of 3.0 V to 3.6 VPCA9515 NXP Semiconductors 2 I C-bus repeater 2 n 5.5 V tolerant I C-bus (SCLn, SDAn) and enable (EN) pins 1 n 0 Hz to 400 kHz clock frequency n ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA n Packages offered: SO8 and TSSOP8 (MSOP8) 3. Ordering information Table 1. Ordering information Type number Package Name Description Version PCA9515D SO8 plastic small outline package 8 leads SOT96-1 body width 3.9 mm 1 PCA9515DP TSSOP8 plastic thin shrink small outline package 8 leads SOT505-1 body width 3 mm 1 Also known as MSOP8. 3.1 Ordering options Table 2. Ordering options Type number Topside mark Temperature range PCA9515D PCA9515 T = - 40 C to +85 C amb PCA9515DP 9515 T = - 40 C to +85 C amb 4. Block diagram V CC PCA9515 SDA0 SDA1 SCL0 SCL1 pull-up resistor EN 002aae620 GND Fig 1. Block diagram of PCA9515 The output pull-down of each internal buffer is set for approximately 0.5 V, while the input threshold of each internal buffer is set about 0.07 V lower, when the output is internally driven LOW. This prevents a lock-up condition from occurring. 1. The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater. PCA9515 9 NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 23 April 2009 2 of 16