PCA9517A 2 Level translating I C-bus repeater Rev. 4.1 24 May 2016 Product data sheet 1. General description The PCA9517A is a CMOS integrated circuit that provides level shifting between low 2 voltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I C-bus or SMBus 2 applications. While retaining all the operating modes and features of the I C-bus system 2 during the level shifts, it also permits extension of the I C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Using the PCA9517A enables the system designer to isolate two halves of a bus for both voltage and capacitance. The SDA and SCL pins are overvoltage tolerant and are high-impedance when the PCA9517A is unpowered. The 2.7 V to 5.5 V bus port B drivers behave much like the drivers on the PCA9515A device, while the adjustable voltage bus port A drivers drive more current and eliminate the static offset voltage. This results in a LOW on the port B translating into a nearly 0 V LOW on the port A which accommodates smaller voltage swings of lower voltage logic. The static offset design of the port B PCA9517A I/O drivers prevent them from being connected to another device that has rise time accelerator including the PCA9510, PCA9511, PCA9512, PCA9513, PCA9514, PCA9515A, PCA9516A, PCA9517A (port B), or PCA9518. Port A of two or more PCA9517As can be connected together, however, to allow a star topography with port A on the common bus, and port A can be connected directly to any other buffer with static or dynamic offset voltage. Multiple PCA9517As can be connected in series, port A to port B, with no build-up in offset voltage with only time of flight delays to consider. The PCA9517A drivers are not enabled unless V is above 0.8 V and V is above CC(A) CC(B) 2.5 V. The EN pin can also be used to turn the drivers on and off under system control. Caution should be observed to only change the state of the enable pin when the bus is idle. The output pull-down on the port B internal buffer LOW is set for approximately 0.5 V, while the input threshold of the internal buffer is set about 70 mV lower (0.43 V). When the port B I/O is driven LOW internally, the LOW is not recognized as a LOW by the input. This prevents a lock-up condition from occurring. The output pull-down on port A drives a hard LOW and the input level is set at 0.3V to accommodate the need for a lower CC(A) LOW level in systems where the low voltage side supply voltage is as low as 0.9 V. Table 1. PCA9517 and PCA9517A comparison 1 2 Parameter PCA9517 PCA9517A electrostatic discharge, HBM > 2 kV > 5.5 kV 1 PCA9517 will be discontinued in several years, so move to the PCA9517A for all new designs and system updates. 2 The PCA9517A is an improved hot swap and ESD version of the PCA9517, but otherwise operates identically and should be used for all new designs and system updates.PCA9517A NXP Semiconductors 2 Level translating I C-bus repeater 2. Features and benefits 2 channel, bidirectional buffer isolates capacitance and allows 400 pF on either side of the device Voltage level translation from 0.9 V to 5.5 V and from 2.7 V to 5.5 V Footprint and functional replacement for PCA9515/15A 2 I C-bus and SMBus compatible Active HIGH repeater enable input Open-drain input/outputs Lock-up free operation Supports arbitration and clock stretching across the repeater 2 Accommodates Standard-mode and Fast-mode I C-bus devices and multiple masters 2 Powered-off high-impedance I C-bus pins Port A operating supply voltage range of 0.9 V to 5.5 V Port B operating supply voltage range of 2.7 V to 5.5 V 2 5V tolerant I C-bus and enable pins 0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater) ESD protection exceeds 5500 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO8, TSSOP8 and HWSON8 3. Ordering information Table 2. Ordering information T = 40 C to +85 C. amb Type number Topside Package mark Name Description Version PCA9517AD PA9517A SO8 plastic small outline package 8 leads body width 3.9 mm SOT96-1 1 PCA9517ADP 9517A TSSOP8 plastic thin shrink small outline package 8 leads SOT505-1 body width 3 mm 1 2 PCA9517ADP/DG 9517A TSSOP8 plastic thin shrink small outline package 8 leads SOT505-1 body width 3 mm PCA9517ATP 17A HWSON8 plastic thermal enhanced very very thin small outline SOT1069-2 package no leads 8 terminals body 2 3 0.8 mm 1 Also known as MSOP8. 2 PCA9517ADP/DG is functionally the same (electrically and mechanically) as the PCA9517ADP, but was initially produced (e.g., born) with Dark Green (lead-free and halogen/antimony-free) package material and is a temporary unique orderable part number for customers who desire to order and only receive Dark Green package material. The standard part PCA9517ADP will transition to Dark Green package material in 2Q12 and then the PCA9517ADP and PCA9517ADP/DG devices will be identical. The PCA9517ADP/DG part number will be EOL after several years as customers who used this temporary part number update their BOM to the normal part number. PCA9517A All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet Rev. 4.1 24 May 2016 2 of 22