PCA9534 2 8-bit I C-bus and SMBus low power I/O port with interrupt Rev. 03 6 November 2006 Product data sheet 1. General description The PCA9534 is a 16-pin CMOS device that provide 8 bits of General Purpose parallel 2 Input/Output (GPIO) expansion for I C-bus/SMBus applications and was developed to 2 enhance the NXP Semiconductors family of I C-bus I/O expanders. The improvements include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O conguration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc. The PCA9534 consists of an 8-bit Conguration register (Input or Output selection) 8-bit Input register, 8-bit Output register and an 8-bit Polarity Inversion register (active HIGH or active LOW operation). The system master can enable the I/Os as either inputs or outputs by writing to the I/O conguration bits. The data for each input or output is kept in the corresponding Input or Output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system 2 master. Although pin-to-pin and I C-bus address compatible with the PCF8574 series, software changes are required due to the enhancements and are discussed in Application Note AN469. The PCA9534 is identical to the PCA9554 except for the removal of the internal I/O pull-up resistor which greatly reduces power consumption when the I/Os are held LOW. The PCA9534 open-drain interrupt output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. 2 Three hardware pins (A0, A1, A2) vary the xed I C-bus address and allow up to eight 2 devices to share the same I C-bus/SMBus. 2. Features 2 n 8-bit I C-bus GPIO n Operating power supply voltage range of 2.3 V to 5.5 V n 5 V tolerant I/Os n Polarity Inversion register n Active LOW interrupt output n Low standby current n Noise lter on SCL/SDA inputs n No glitch on power-up n Internal power-on resetPCA9534 NXP Semiconductors 2 8-bit I C-bus and SMBus low power I/O port with interrupt n 8 I/O pins which default to 8 inputs n 0 Hz to 400 kHz clock frequency n ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA n Offered in four different packages: SO16, TSSOP16, and HVQFN16 (4 4 0.85 mm and 3 3 0.85 mm versions) 3. Ordering information Table 1. Ordering information T = - 40 C to +85 C. amb Type number Topside Package mark Name Description Version PCA9534D PCA9534D SO16 plastic small outline package 16 leads body width 7.5 mm SOT162-1 PCA9534PW PCA9534 TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm PCA9534BS 9534 HVQFN16 plastic thermal enhanced very thin quad at package SOT629-1 no leads 16 terminals body 4 4 0.85 mm PCA9534BS3 P34 HVQFN16 plastic thermal enhanced very thin quad at package SOT758-1 no leads 16 terminals body 3 3 0.85 mm 4. Block diagram PCA9534 A0 IO0 A1 IO1 A2 8-bit IO2 SCL INPUT INPUT/ 2 IO3 I C-BUS/SMBus SDA FILTER OUTPUT CONTROL IO4 PORTS write pulse IO5 IO6 read pulse V DD POWER-ON IO7 RESET V DD V SS INT LP FILTER 002aac469 All I/Os are set to inputs at reset. Fig 1. Block diagram of PCA9534 PCA9534 3 NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 6 November 2006 2 of 25