89PES5T5 5-Lane 5-Port PCI Express Data Sheet Switch u Highly Integrated Solution Device Overview Requires no external components The 89HPES5T5 is a member of IDTs PRECISE family of PCI Incorporates on-chip internal memory for packet buffering and Express switching solutions. The PES5T5 is an 5-lane, 5-port peripheral queueing chip that performs PCI Express Base switching. It provides connectivity Integrates five 2.5 Gbps embedded SerDes with 8B/10B and switching functions between a PCI Express upstream port and up to encoder/decoder (no separate transceivers needed) four downstream ports and supports switching between downstream u Reliability, Availability, and Serviceability (RAS) Features ports. Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end Features CRC (ECRC) u High Performance PCI Express Switch Supports ECRC and Advanced Error Reporting Five 2.5Gbps PCI Express lanes Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O Five switch ports Compatible with Hot-Plug I/O expanders used on PC mother- Upstream port is x1 boards u Downstream ports are x1 Power Management Low-latency cut-through switch architecture Utilizes advanced low-power design techniques to achieve low Support for Max Payload Sizes up to 256 bytes typical power consumption One virtual channel Supports PCI Power Management Interface specification (PCI- Eight traffic classes PM 1.2) PCI Express Base Specification Revision 1.1 compliant Unused SerDes are disabled. u Flexible Architecture with Numerous Configuration Options Supports Advanced Configuration and Power Interface Speci- fication, Revision 2.0 (ACPI) supporting active link state Automatic lane reversal on all ports u Testability and Debug Features Automatic polarity inversion Ability to load device configuration from serial EEPROM Built in Pseudo-Random Bit Stream (PRBS) generator u Legacy Support Numerous SerDes test modes Ability to read and write any internal register via the SMBus PCI compatible INTx emulation Ability to bypass link training and force any link into any mode Bus locking Provides statistics and performance counters Block Diagram 5-Port Switch Core / 5 PCI Express Lanes Port Frame Buffer Route Table Scheduler Arbitration Transaction Layer Transaction Layer Transaction Layer Transaction Layer Transaction Layer Data Link Layer Data Link Layer Data Link Layer Data Link Layer Data Link Layer Mux / Demux Mux / Demux Mux / Demux Mux / Demux Mux / Demux Phy Phy Phy Phy Phy Logical Logical Logical Logical Logical Layer Layer Layer Layer Layer SerDes SerDes SerDes SerDes SerDes (Port 0) (Port 2) (Port 3) (Port 4) (Port 5) Figure 1 Internal Block Diagram IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 28 June 18, 2014IDT 89PES5T5 Data Sheet u 11 General Purpose Input/Output Pins Each pin may be individually configured as an input or output Each pin may be individually configured as an interrupt input Some pins have selectable alternate functions u Packaged in a 15mm x 15mm 196-ball BGA with 1mm ball spacing Product Description Utilizing standard PCI Express interconnect, the PES5T5 provides the most efficient I/O connectivity solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. It provides 2.5 GBps (20 Gbps) of aggregated, full-duplex switching capacity through 5 integrated serial lanes, using proven and robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in both direc- tions and is fully compliant with PCI Express Base specification revision 1.1. The PES5T5 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transac- tion layers in compliance with PCI Express Base specification Revision 1.1. The PES5T5 can operate either as a store and forward or cut-through switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management to allow efficient switching for applications requiring additional narrow port connectivity. Processor Processor Memory North Memory Memory Memory Bridge South Bridge x1 PES5T5 x1 x1 x1 x1 GE GE 1394 GE LOM LOM Figure 2 I/O Expansion Application SMBus Interface The PES5T5 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES5T5, allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register values of the PES5T5 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O expander. Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in Table 1. 2 of 28 June 18, 2014