89HPES6T6G2 6-Lane 6-Port Data Sheet Gen2 PCI Express Switch Configurable downstream port PCI-to-PCI bridge device Device Overview numbering The 89HPES6T6G2, a 6-lane 6-port Gen2 PCI Express switch, is a Crosslink support member of IDTs PRECISE family of PCI Express switching solutions. Supports ARI forwarding defined in the Alternative Routing-ID The PES6T6G2 is a peripheral chip that performs PCI Express Base Interpretation (ARI) ECN for virtualized and non-virtualized switching with a feature set optimized for servers, storage, communica- environments tions, and consumer applications. It provides connectivity and switching Ability to load device configuration from serial EEPROM functions between a PCI Express upstream port and five downstream Legacy Support ports or peer-to-peer switching between downstream ports. PCI compatible INTx emulation Supports bus locked transactions, allowing use of PCI Express Features with legacy software High Performance PCI Express Switch Highly Integrated Solution Six Gen2 PCI Express lanes supporting 5 Gbps and 2.5 Gbps operation Requires no external components One x1 upstream port Incorporates on-chip internal memory for packet buffering and queueing Five x1 downstream ports Integrates six 5 Gbps / 2.5 Gbps embedded SerDes, 8B/10B Low latency cut-through switch architecture encoder/decoder (no separate transceivers needed) Support for Max Payload Size up to 2Kbytes Reliability, Availability, and Serviceability (RAS) Features Supports one virtual channel and eight traffic classes Ability to disable peer-to-peer communications PCI Express Base Specification Revision 2.0 compliant Supports ECRC and Advanced Error Reporting Flexible Architecture with Numerous Configuration Options All internal data and control RAMs are SECDED ECC Automatic lane reversal on all ports protected Automatic polarity inversion Supports PCI Express hot-plug on all downstream ports Supports in-band hot-plug presence detect capability Supports upstream port hot-plug Supports external signal for hot plug event notification allowing Hot-swap capable I/O SCI/SMI generation for legacy operating systems External Serial EEPROM contents are checksum protected Block Diagram 6-Port Switch Core / 6 Gen2 PCI Express Lanes Port Frame Buffer Route Table Scheduler Arbitration Transaction Layer Transaction Layer Transaction Layer Data Link Layer Data Link Layer Data Link Layer Multiplexer / Demultiplexer Multiplexer / Demultiplexer Multiplexer / Demultiplexer Phy Phy Phy Logical Logical Logical Layer Layer Layer SerDes SerDes SerDes (Port 1) (Port 5) (Port 0) Figure 1 Internal Block Diagram IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 30 March 30, 2011 DSC 6930 2011 Integrated Device Technology, Inc.IDT 89HPES6T6G2 Data Sheet Supports PCI Express Device Serial Number Capability tions. It supports eight Traffic Classes (TCs) and one Virtual Channel Capability to monitor link reliability and autonomously change (VC) with sophisticated resource management to enable efficient link speed to prevent link instability switching and I/O connectivity for servers, storage, and embedded Power Management processors with limited connectivity. Utilizes advanced low-power design techniques to achieve low typical power consumption Support PCI Power Management Interface specification (PCI- Processor Processor PM 2.0) Supports device power management states: D0, D3 and hot D3 cold Memory Support for PCI Express Active State Power Management North Memory Memory Memory Bridge (ASPM) link state Supports link power management states: L0, L0s, L1, L2/L3 x1 Ready and L3 Supports PCI Express Power Budgeting Capability PES6T6G2 Configurable SerDes power consumption Supports optional PCI-Express SerDes Transmit Low-Swing x1 x1 x1 x1 x1 Voltage Mode Supports numerous SerDes Transmit Voltage Margin I/O I/O I/O I/O settings PCI Express 4xGbE 4xGbE SATA SATA Slots Unused SerDes are disabled Testability and Debug Features Figure 2 I/O Expansion Application Per port link up and activity status outputs available on I/O expander outputs SMBus Interface Built in SerDes 8-bit and 10-bit pseudo-random bit stream (PRBS) generators The PES6T6G2 contains two SMBus interfaces. The slave interface Numerous SerDes test modes, including a PRBS Master provides full access to the configuration registers in the PES6T6G2, Loopback mode for in-system link testing allowing every configuration register in the device to be read or written Ability to read and write any internal register via SMBus and by an external agent. The master interface allows the default configura- JTAG interfaces, including SerDes internal controls tion register values of the PES6T6G2 to be overridden following a reset Per port statistics and performance counters, as well as propri- with values programmed in an external serial EEPROM. The master etary link status registers interface is also used by an external Hot-Plug I/O expander. Seven General Purpose Input/Output Pins Two pins make up each of the two SMBus interfaces. These pins Each pin may be individually configured as an input or output consist of an SMBus clock pin and an SMBus data pin.The Master Each pin may be individually configured as an interrupt input SMBus address is hardwired to 0x50, and the slave SMBus address is Some pins have selectable alternate functions hardwired to 0x77. Packaged in a 19mm x 19mm 324-ball Flip Chip BGA with As shown in Figure 3, the master and slave SMBuses may be used 1mm ball spacing in a unified or split configuration. In the unified configuration, shown in Figure 3(a), the master and slave SMBuses are tied together and the Product Description PES6T6G2 acts both as a SMBus master as well as a SMBus slave on Utilizing standard PCI Express interconnect, the PES6T6G2 this bus. This requires that the SMBus master or processor that has provides the most efficient I/O connectivity solution for applications access to PES6T6G2 registers supports SMBus arbitration. In some requiring high throughput, low latency, and simple board layout with a systems, this SMBus master interface may be implemented using minimum number of board layers. It provides connectivity for up to 6 general purpose I/O pins on a processor or micro controller, and may ports across 6 integrated serial lanes. Each lane provides 5 Gbps of not support SMBus arbitration. To support these systems, the bandwidth in both directions and is fully compliant with PCI Express PES6T6G2 may be configured to operate in a split configuration as Base Specification, Revision 2.0, including operation in 5 Gbps, 2.5 shown in Figure 3(b). Gbps, and mixed 5 Gbps / 2.5Gbps modes. In the split configuration, the master and slave SMBuses operate as The PES6T6G2 is based on a flexible and efficient layered architec- two independent buses and thus multi-master arbitration is never ture. The PCI Express layer consists of SerDes, Physical, Data Link and required. The PES6T6G2 supports reading and writing of the serial Transaction layers in compliance with PCI Express Base specification EEPROM on the master SMBus via the slave SMBus, allowing in Revision 2.0. The PES6T6G2 can operate either as a store and forward system programming of the serial EEPROM. or cut-through switch and is designed to switch memory and I/O transac- 2 of 30 March 30, 2011