Version 1.2 2005 . PEX 8311 PCI Express to Generic Local Bus Bridge Features Multi-purpose and Feature-Rich PCI Express Bridge PEX 8311 Key Features The bridge offers PCI Express (PCIe) bridging capability from a Generic o PCI Express to Generic Local Bus Bridge Local Bus to PCIe enabling users to add scalable high bandwidth o Root Complex and EndPoint Modes of interconnection to a wide variety of applications including communication Operation line cards, surveillance systems, video capture cards, industrial control, office o Local Bus modes: - 32-bit address & 32-bit data C Mode automation, IP Media Servers, RAID systems and medical imaging. Many - Multiplexed 32-bit address/data J Mode embedded system designs utilizing PCI today can easily migrate to PCIe. The o Local Bus Clock rates to 66MHz ExpressLane PEX 8311 bridge can be used in Root Complex mode with the o Zero wait state bursts to 264 MB/sec device directly interfacing multiple local bus devices including processors and o 1 Lane PCI Express Port o 2 DMA Channels FPGAs to a downstream PCIe port. The bridge can also function in an EndPoint o Integrated SerDes type application connecting multiple local bus components to an upstream PCIe o 21mmx21mm, 337 pin PBGA package port. o 3.3V I/O and 5V tolerant Local Bus o Power: 1.0 Watt Highly Flexible, Generic Local Bus PEX 8311 Additional Features The PEX 8311 offers a highly flexible yet low overhead generic Local Bus o Integrated PCI Express Interface - Compliant to PCIe Specification, r1.0a which provides a direct connection to two generic industry-standard - x1 Link, dual-simplex, 2.5 Gbps/direction interconnect buses. The bus protocol can be set to the non-multiplexed - Auto Polarity reversal address and data mode with up to 32-bit transfers C-Mode or multiplexed - 128 Byte payload maximum address/data with up to 32-bit transfers J-Mode. This bus can be directly - Link CRC support connected to many processors with minimal or no glue logic. Memory, - Link/Device power management - Flow control buffering FPGAs, FIFOs and other devices can be simultaneously placed on this bus. - PCIe transaction queues for eight outstanding TLPs Dual Independent DMA Channels o VGA/ISA Enable Registers The PEX 8311 provides two data transfer channels each with internal o On-the-fly Endian conversion independent programmable FIFOs. These channels provide independent data o Multiple DMA operational modes - Block and scatter/gather transfers transfers with the bridge initiating both the PCIe and local bus. With dual - DMA descriptor ring management channels, data from two different sources or bidirectional traffic can be - Demand mode & EOT H/W controls transferred simultaneously without the need to finish one transfer before o Direct Master data transfers starting the second. Each DMA channel can use independent scatter-gather - Read ahead and programmable read pre- fetch counter descriptor lists for increased flexibility. The use of DMA descriptors allows - Generate any PCIe transaction the two channels to look like multiple virtual DMA channels. o Direct Slave data transfers - 8-,16-, and 32-bit local bus access Complete Conversion from PCI Express Signaling - Writes, read ahead, posted writes, The PEX 8311 provides a complete local bus to PCIe translation. The bridge programmable read pre-fetch counter o Control is equipped with a standard PCIe port that operates as a single x1 link with a - Eight mailbox and two doorbell registers maximum of 250 Megabytes per second of throughput per transmit and - Root Complex or EndPoint mode receive directions. The single 2.5 Gbps integrated SerDes delivers the highest reset/interrupt bandwidth with the lowest possible pin-count. The device supports internal - Serial EEPROM Interface - DC JTAG Boundary Scan queues with flow control features to optimize throughput and traffic flow. - Four GPIO Pins, 1 GPO, 1 GPI - I2O Messaging Unit Root Complex and EndPoint Modes The PEX 8311 bridge supports both Root Complex and EndPoint modes of operation. This flexibility allows a Root Complex system designer to utilize the part as a type of north bridge whereby multiple Local Bus components present including a processor, FPGAs, memory, DSP, etc., can communicate with each other as well with downstream PCIe devices. In this case, the bridges configuration and system hierarchy comes through the Local Bus. In EndPoint mode, the bridge is configured through the PCIe port.Direct Master or Direct Slave Operation generation, unaligned Local Bus transfers of any byte length, on-the-fly Local Bus Endian conversion, The PEX 8311 bridge provides master (Upstream traffic programmable Local Bus wait states, and Local Bus parity generation) and slave (Downstream traffic acceptance) checking. General purpose messaging for proprietary capability. These transfers can occur simultaneously message schemes include: eight 32-bit registers for with the DMA transfers and are given priority. For polled topologies and two 32-bit doorbell registers for master mode requests, the bridge services local bus interrupt driven environments. masters by generating Upstream traffic on the PCIe side. There are two local bus address space maps to PCIe Fully Compliant Power Management (Direct Master mode): one to memory and one to I/O For applications that require power management, the with the bridge generating PCIe memory and I/O PEX 8311 device supports both link (L0, L0s, L1, L2/L3 transaction types. The bridge has independent large Ready, and L3) and device (D0, D1, D2 and D3) power depth Read and Write FIFOs. Read ahead and management states, in compliance with the PCIe power programmable read pre-fetch counters enhance management specification. Full power management performance. Register configuration is through the PCIe event packets are generated and received and translated port, Local Bus or through an optional EEPROM. to local bus signaling. The PEX 8311 also supports direct slave requests where PLX I/O Accelerator Compatibility the bridge services PCIe side Downstream traffic The PEX 8311 is Register compatible with existing initiators by mastering the Local Bus side. The bridge PLXs bus mastering Local Bus to PCI bridging has two general purpose address spaces and one solutions (PLX PCI 9000 series). For many designs Expansion ROM space that could be used as a general migrating from PCI to PCIe, existing code utilizing these purpose direct slave space map to the Local Bus. Each I/O Accelerators can be used. As PCIe and PCI are address space may be configured for 8-, 16-, or 32-bit compatible, designs can quickly be extended to take Local Bus data widths for flexible connectivity to Local advantage of PCI Express bandwidth, system control, Bus devices. Independent Read and Write FIFOs of large and data integrity. depth provide buffering. Performance is enhanced through deferred writes, posted writes, read ahead, and programmable read pre-fetch counters. Internal Block Diagram Figure 1 below shows an overview of the PEX 8311 Hardware DMA Controls-EOT /Demand Mode Bridge. The device provides for full FIFO memory To optimize data transfers in many applications, buffers for each DMA channel and for Direct Master and particularly communications, the PEX 8311 supports Direct Slave operation. A complete three layer PCIe hardware based control signals. When End of Transfer protocol interface with integrated SerDes provides (EOT ) is asserted, the bridge immediately terminates conversion from local bus data to/from PCI Express port the current transfer and indicates the number of bytes transfers. Modules for Hot Plug and power management transferred. Along with unlimited bursting capability, are included. Two serial EEPROM interfaces allow an EOT is useful in applications where the lengths of the additional configuration option. read packets are not known until the packets are read. Figure 1. High-Speed Data Transfers Additional hardware signaling control based DMA Serial EEPROM Serial EEPROM transfers are available. Serial Serial EEPROM EEPROM With Demand Mode each DMA channel has a pair of Interface Interface hardware signals that are used to pause and resume the current transfer. This allows a peripheral device such as PCI Express Local Bus Generic PCI Express Bus Configuration Local Bus a line card with its own FIFO to control DMA transfers. Configuration Interface Registers Interface Registers This mode can be used on many non-FIFO transfers as well in a variety of end applications. FIFOs Advanced Performance Features Hot Plug Power PCI Express Management The PEX 8311 has a variety of added capabilities which enhance throughput and flexibility for all transfer types: Applications DMA, Direct Master and Direct Slave. These include zero wait state local bus bursts to 264 MB/s with Suitable for Root Complex-centric as well as EndPoint programmable burst lengths including unlimited I/O applications, the PEX 8311 can be configured for a bursting, deep FIFO for maximum PCIe packet wide variety of form factors and applications. PCI Express Generic Local Bus