VERSION 1.0 2002 PCI 9656 Connectivity 64-bit, 66MHz PCI Bus Mastering I/O Accelerator for Motorola 64-bit, 66MHz PCI r2.2 compliant PowerQUICC & Generic 32-bit, 66MHz Local Bus Designs Motorola PowerQUICC and generic 32-bit, 66MHz local bus modes Maximum PCI Bandwidth for Your 32-bit Local Bus Applications 3.3V I/O, 5V tolerant bus interfaces The PCI 9656 offers flexible connectivity and high performance I/O acceleration features PICMG 2.1 r2.0 Hot Swap Silicon to enable leading edge PCI, CompactPCI, and embedded host designs. 272-ball, 27 x 27 mm, 1.27 mm Motorola MPC 850/860 PowerQUICC Designs pitch PBGA The PCI 9656 is the perfect match for the industry leading 32-bit communication proces- sor, the Motorola MPC 850/860 PowerQUICC. The PCI 9656 provides a direct connection Performance to PowerQUICC devices, enabling high-speed 64-bit, 66MHz PCI performance with its Zero wait state burst operation Data Pipe Architecture technology. PCI bus bursts to 528 MB/sec Generic 32-bit, 66MHz Local Bus Designs Local bus bursts to 264 MB/sec The PCI 9656 provides direct connection to two generic industry standard interconnect 2 DMA Channels buses. Designers use these 32-bit, 66MHz buses for a myriad of high-speed devices rang- Block and Scatter/Gather transfers ing from processors, to DSPs, to memories, to custom ASICs and FPGAs. DMA descriptor ring management The PCI 9656 Data Pipe Architecture technology enables high-speed, 64-bit, 66MHz PCI Demand Mode and EOT I/O with those devices. Hardware controls Move Your 32-bit Local Bus Designs Up to Direct Master data transfers 64-bit, 66MHz PCI Operation Generate any PCI transaction As PCI evolves to meet the ever increasing I/O demands of leading edge systems, PLX Read ahead and programmable continues to provide leading edge, high performance PCI I/O acceleration solutions. Based read prefetch counter on the architecture of the industry-leading PCI 9054, the PCI 9656 offers a variety of Direct Slave data transfers enhancements for the needs of today s telecom, networking, and I/O adapter designs: Access 8-, 16-, and 32-bit local 64-bit, 66MHz PCI operation bus devices 32-bit, 66MHz local bus operation Deferred reads, deferred writes, Dynamic DMA descriptor ring management with Valid bit semaphore control read ahead, posted writes, pro- grammable read prefetch counter PICMG 2.1 r2.0 Hot Swap Silicon, including Bias Voltage, Early Power, 64-bit Initialization, and Intially Not Responding Support Control PCI Power Management r1.1 D3 Power Management Event (PME) generation COLD I O r1.5 messaging unit 2 PCI arbiter supporting 7 external masters Eight mailbox and two Reset and interrupt pins configurable for embedded host applications doorbell registers PCI arbiter supports 7 JTAG boundary scan external masters The PCI 9656 is register compatible with the PCI 9054, enabling easy software migration. Host mode reset/interrupt signal configuration PCI D3 Power Management COLD Event (PME) generation support Serial EEPROM interface JTAG boundary scan PCI 9656 Features Serial EEPROM Independent 16 Qword (128 byte) read Store configuration register power on, and 32 Qword (256 byte) write FIFOs The PCI 9656 64-bit, 66MHz PCI I/O accelera- reset values Deferred reads, deferred writes, posted tor is the most advanced, general-purpose An alternative to expansion ROM for stor- writes, read ahead, and programmable read bus mastering device available for Motorola ing Vital Product Data (VPD) prefetch counter MPC 850/860 PowerQUICC and generic Supports 2 Kbit/4 Kbit microwire devices Programmable READY time out 32-bit, 66MHz local bus based designs. The with sequential read and recovery PCI 9656 incorporates PLXs industry leading Advanced Performance Features Common to Data Pipe Architecture technology, featuring Data Pipe Architecture DMA, Direct Master, and Direct Slave DMA engines, programmable Direct Master DMA Zero wait state PCI & local bus bursts and Direct Slave data transfer modes, and PCI Service DMA descriptors, mastering on both Deep FIFOs prolong bursts messaging functions. bus interfaces during data transfer Unaligned PCI and local bus transfers of Two independent channels provide flexible Interfaces any byte length prioritization scheme PCI On-the-fly Endian conversion Each channel has its own bi-directional 64-bit, 66MHz r2.2 operation 32 Qword (256 byte) deep FIFO Programmable local bus wait states Zero wait state bursts to 528 MB/s Block Mode services a single DMA Parity checking on both buses Dual Address Cycle (DAC) support as a descriptor in PCI 9656 registers Messaging PCI bus master Scatter/Gather Mode services DMA Provides industry standard I O r1.5 2 Vital Product Data (VPD) descriptor linked lists in memory messaging unit 3.3V I/O, 5V tolerant Burst descriptors from PCI or local Supports general-purpose messaging bus memory PICMG 2.1 r2.0 Hot Swap Silicon for proprietary message schemes Programming Interface 0 (P=0) Descriptor lists either linear (static) or Eight 32-bit mailbox registers for polled circular (dynamic) with Valid bit sema- environments Bias Voltage Support phore control Two 32-bit doorbell register for interrupt Early Power Support Direct Hardware DMA controls driven environments Initially Not Responding Support Demand Mode to pause/resume Embedded Host Features PCI Hot Plug r1.0 End of Transfer (EOT) to abort PCI arbiter supports 7 external masters PCI Power Management r1.1 Programmable local bus burst length, Reset and interrupt signals configurable for Supports D0, D1, D2, D3 , & D3 including infinite HOT COLD embedded host operation power states Enhanced M Mode supports bursts beyond Type 0/1 Configuration support allows D3 Power Management Event (PME) PowerQUICC 16 byte limit COLD local bus master to configure PCI bus generation to meet PC 2001 Windows and devices Direct Master 98/2000 communication adapter logo Service local bus masters by mastering on certification requirements Package the PCI bus Local Bus 272-pin PBGA Two local bus address spaces map to PCI Three local bus options on the device 27 mm x 27 mm, 1.27 mm ball pitch bus: one to memory one to I/O M Mode: Motorola MPC 850/860 Low power 2.5V CMOS core Generate all PCI memory and I/O PowerQUICC and PowerPC 80x/82x transaction types, including Memory 3.3V I/O, 5V tolerant C Mode: De-multiplexed address and data Write and Invalidate (MWI) Industrial temperature range operation buses for Intel i960 , DSPs, custom ASICs Independent 16 Qword (128 byte) read and FPGAs, and others IEEE 1149.1 JTAG boundary scan and 32 Qword (256 byte) write FIFOs J Mode: Multiplexed address and data Backward Compatibility Read ahead and programmable read buses for Intel i960, IBM PowerPC 401, IDT prefetch counter The PCI 9656 register set is backward RC32364, DSPs, IOP 480, and others compatible with the PCI 9054, with new PowerQUICC deferred reads and IDMA 32-bit, 66MHz operation registers added for the new functionality (M mode only) Zero wait state bursts to 264 MB/s enhancements Direct Slave 3.3V I/O, 5V tolerant Related PLX Products Service PCI bus masters by mastering on the Asynchronous clock inputs to PCI Support for 32-bit, 66MHz PCI with 32-bit, local bus and local bus 66MHz C, J, and M Local Bus support is Two general-purpose and one expansion provided by the PCI 9056 ROM PCI address spaces map to local See the PCI 9056 product brief for details bus memory Each address space may specify 8-, 16-, or 32-bit local bus data transfer