89HPES12T3G2 12-Lane 3-Port Data Sheet Gen2 PCI Express Switch Legacy Support Device Overview PCI compatible INTx emulation The 89HPES12T3G2 is a member of IDTs PRECISE family of PCI Express switching solutions. The PES12T3G2 is a 12-lane, 3-port Bus locking Gen2 peripheral chip that performs PCI Express Base switching with a Highly Integrated Solution feature set optimized for high performance applications such as servers, Incorporates on-chip internal memory for packet buffering and storage, and communications/networking. It provides connectivity and queueing switching functions between a PCI Express upstream port and two Integrates twelve 5 Gbps embedded SerDes with 8b/10b downstream ports and supports switching between downstream ports. encoder/decoder (no separate transceivers needed) Receive equalization (RxEQ) Features Reliability, Availability, and Serviceability (RAS) Features High Performance PCI Express Switch Internal end-to-end parity protection on all TLPs ensures data Twelve 5 Gbps Gen2 PCI Express lanes integrity even in systems that do not implement end-to-end Three switch ports CRC (ECRC) One x4 upstream port Supports ECRC and Advanced Error Reporting Two x4 downstream ports Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O Low latency cut-through switch architecture Compatible with Hot-Plug I/O expanders used on PC mother- Support for Max Payload Size up to 2048 bytes boards One virtual channel Supports Hot-Swap Eight traffic classes PCI Express Base Specification Revision 2.0 compliant Flexible Architecture with Numerous Configuration Options Automatic per port link width negotiation to x4, x2 or x1 Automatic lane reversal on all ports Automatic polarity inversion Ability to load device configuration from serial EEPROM Block Diagram 3-Port Switch Core / 12 PCI Express Lanes Port Frame Buffer Route Table Scheduler Arbitration Transaction Layer Transaction Layer Transaction Layer Data Link Layer Data Link Layer Data Link Layer Multiplexer / Demultiplexer Multiplexer / Demultiplexer Multiplexer / Demultiplexer Phy Phy Phy Logical Logical Logical Layer Layer Layer SerDes SerDes SerDes (Port 0) (Port 2) (Port 4) Figure 1 Internal Block Diagram IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 30 August 10, 2011 DSC 6930IDT 89HPES12T3G2 Data Sheet Power Management Utilizes advanced low-power design techniques to achieve low typical power consumption Processor Processor Support PCI Express Power Management Interface specifica- tion (PCI-PM 1.2) Supports PCI Express Active State Power Management Memory North Memory Memory (ASPM) link state Memory Bridge Supports PCI Express Power Budgeting Capability x4 Supports the optional PCI Express SerDes Transmit Low- Swing Voltage Mode PES12T3G2 Unused SerDes are disabled and can be powered-off. Testability and Debug Features x4 x4 x4 Built in Pseudo-Random Bit Stream (PRBS) generator Numerous SerDes test modes I/O I/O I/O Ability to read and write any internal register via the SMBus PCI Express 10GbE 10GbE SATA Slot Ability to bypass link training and force any link into any mode Provides statistics and performance counters Figure 2 I/O Expansion Application Nine General Purpose Input/Output Pins Each pin may be individually configured as an input or output SMBus Interface Each pin may be individually configured as an interrupt input The PES12T3G2 contains two SMBus interfaces. The slave inter- Some pins have selectable alternate functions face provides full access to the configuration registers in the Packaged in a 19mm x 19mm 324-ball BGA with 1mm ball PES12T3G2, allowing every configuration register in the device to be spacing read or written by an external agent. The master interface allows the default configuration register values of the PES12T3G2 to be over- Product Description ridden following a reset with values programmed in an external serial Utilizing standard PCI Express interconnect, the PES12T3G2 EEPROM. The master interface is also used by an external Hot-Plug I/O provides the most efficient fan-out solution for applications requiring high expander. throughput, low latency, and simple board layout with a minimum Six pins make up each of the two SMBus interfaces. These pins number of board layers. It provides 12 GBps (96 Gbps) of aggregated, consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus full-duplex switching capacity through 12 integrated serial lanes, using address pins. In the slave interface, these address pins allow the proven and robust IDT technology. Each lane provides 5 Gbps of band- SMBus address to which the device responds to be configured. In the width in both directions and is fully compliant with PCI Express Base master interface, these address pins allow the SMBus address of the Specification, Revision 2.0. serial configuration EEPROM from which data is loaded to be config- The PES12T3G2 is based on a flexible and efficient layered architec- ured. The SMBus address is set up on negation of PERSTN by ture. The PCI Express layer consists of SerDes, Physical, Data Link and sampling the corresponding address pins. When the pins are sampled, Transaction layers in compliance with PCI Express Base specification the resulting address is assigned as shown in Table 1. Revision 2.0. The PES12T3G2 can operate either as a store and forward or cut-through switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Slave Master Channel (VC) with sophisticated resource management to enable effi- Bit SMBus SMBus cient switching and I/O connectivity for servers, storage, and embedded Address Address processors with limited connectivity. 1 SSMBADDR 1 MSMBADDR 1 2 SSMBADDR 2 MSMBADDR 2 3 SSMBADDR 3 MSMBADDR 3 4 0 MSMBADDR 4 5 SSMBADDR 5 1 61 0 71 1 Table 1 Master and Slave SMBus Address Assignment 2 of 30 August 10, 2011