89HPES24NT24G2 24-Lane 24-Port PCIe Gen2 Datasheet System Interconnect Switch Movable upstream port within and between switch partitions Device Overview Non-Transparent Bridging (NTB) Support The 89HPES24NT24G2 is a member of the IDT family of PCI Supports up to 8 NT endpoints per switch, each endpoint can Express switching solutions. The PES24NT24G2 is a 24-lane, 24-port communicate with other switch partitions or external PCIe system interconnect switch optimized for PCI Express Gen2 packet domains or CPUs switching in high-performance applications, supporting multiple simulta- 6 BARs per NT Endpoint neous peer-to-peer traffic flows. Target applications include multi-host or Bar address translation intelligent I/O based systems where inter-domain communication is All BARs support 32/64-bit base and limit address translation required, such as servers, storage, communications, and embedded Two BARs (BAR2 and BAR4) support look-up table based systems. address translation Features 32 inbound and outbound doorbell registers High Performance Non-Blocking Switch Architecture 4 inbound and outbound message registers 24-lane, 24-port PCIe switch with flexible port configuration Supports up to 64 masters Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s Unlimited number of outstanding transactions Gen1 operation Multicast Delivers up to 24 GBps (192 Gbps) of switching capacity Compliant with the PCI-SIG multicast Supports 128 Bytes to 2 KB maximum payload size Supports 64 multicast groups Low latency cut-through architecture Supports multicast across non-transparent port Supports one virtual channel and eight traffic classes Multicast overlay mechanism support Port Configurability ECRC regeneration support Twenty-four x1 ports configurable as follows: Integrated Direct Memory Access (DMA) Controllers One x8 stack Supports up to 2 DMA upstream ports, each with 2 DMA chan- Eight x1 ports (ports 0 through 7 are not capable of nels merging with an adjacent port) Supports 32-bit and 64-bit memory-to-memory transfers Two x8 stacks configurable as: Fly-by translation provides reduced latency and increased Two x8 ports performance over buffered approach Four x4 ports Supports arbitrary source and destination address alignment Eight x2 ports Supports intra- as well as inter-partition data transfers using Sixteen x1 ports the non-transparent endpoint Automatic per port link width negotiation Supports DMA transfers to multicast groups (x8 x4 x2 x1) Linked list descriptor-based operation Crosslink support Flexible addressing modes Automatic lane reversal Linear addressing Per lane SerDes configuration Constant addressing De-emphasis Quality of Service (QoS) Receive equalization Port arbitration Drive strength Round robin Innovative Switch Partitioning Feature Request metering Supports up to 8 fully independent switch partitions IDT proprietary feature that balances bandwidth among Logically independent switches in the same device switch ports for maximum system throughput Configurable downstream port device numbering High performance switch core architecture Supports dynamic reconfiguration of switch partitions Combined Input Output Queued (CIOQ) switch architecture Dynamic port reconfiguration downstream, upstream, with large buffers non-transparent bridge Dynamic migration of ports between partitions IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 35 December 17, 2013 2013 Integrated Device Technology, IncIDT 89HPES24NT24G2 Datasheet Clocking 9 General Purpose I/O Supports 100 MHz and 125 MHz reference clock frequencies Test and Debug Flexible port clocking modes Ability to inject AER errors simplifies in system error handling software validation Common clock Non-common clock On-chip link activity and status outputs available for several ports Local port clock with SSC (spread spectrum setting) and port reference clock input Per port link activity and status outputs available using 2 external I C I/O expander for all remaining ports Hot-Plug and Hot Swap Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG Hot-plug controller on all ports Standards and Compatibility Hot-plug supported on all downstream switch ports 2 PCI Express Base Specification 2.1 compliant All ports support hot-plug using low-cost external I C I/O expanders Implements the following optional PCI Express features Configurable presence-detect supports card and cable appli- Advanced Error Reporting (AER) on all ports cations End-to-End CRC (ECRC) GPE output pin for hot-plug event notification Access Control Services (ACS) Enables SCI/SMI generation for legacy operating system Device Serial Number Enhanced Capability support Sub-System ID and Sub-System Vendor ID Capability Hot-swap capable I/O Internal Error Reporting Power Management Multicast Supports D0, D3hot and D3 power management states VGA and ISA enable Active State Power Management (ASPM) L0s and L1 ASPM Supports L0, L0s, L1, L2/L3 Ready, and L3 link states ARI Configurable L0s and L1 entry timers allow performance/ Power Supplies power-savings tuning Requires three power supply voltages (1.0V, 2.5V, and 3.3V) SerDes power savings Packaged in a 19mm x 19mm 324-ball Flip Chip BGA with Supports low swing / half-swing SerDes operation 1mm ball spacing SerDes associated with unused ports are turned off SerDes associated with unused lanes are placed in a low Product Description power state With Non-Transparent Bridging functionality and innovative Switch Reliability, Availability, and Serviceability (RAS) Partitioning feature, the PES24NT24G2 allows true multi-host or multi- ECRC support processor communications in a single device. Integrated DMA control- AER on all ports lers enable high-performance system design by off-loading data transfer SECDED ECC protection on all internal RAMs operations across memories from the processors. Each lane is capable End-to-end data path parity protection of 5 GT/s link speed in both directions and is fully compliant with PCI Express Base Specification 2.1. Checksum Serial EEPROM content protected Ability to generate an interrupt (INTx or MSI) on link up/down A non-transparent bridge (NTB) is required when two PCI Express transitions domains need to communicate to each other. The main function of the Initialization / Configuration NTB block is to initialize and translate addresses and device IDs to Supports Root (BIOS, OS, or driver), Serial EEPROM, or allow data exchange across PCI Express domains. The major function- SMBus switch initialization alities of the NTB block are summarized in Table 1. Common switch configurations are supported with pin strap- ping (no external components) Supports in-system Serial EEPROM initialization/program- ming On-Die Temperature Sensor Range of 0 to 127.5 degrees Celsius Three programmable temperature thresholds with over and under temperature threshold alarms Automatic recording of maximum high or minimum low temperature 2 of 35 December 17, 2013