89HPES32NT24BG2 32-Lane 24-Port PCIe Gen2 Datasheet System Interconnect Switch Dynamic port reconfiguration downstream, upstream, Device Overview non-transparent bridge The 89HPES32NT24BG2 is a member of the IDT family of PCI Dynamic migration of ports between partitions Express switching solutions. The PES32NT24BG2 is a 32-lane, 24- Movable upstream port within and between switch partitions port system interconnect switch optimized for PCI Express Gen2 packet Non-Transparent Bridging (NTB) Support switching in high-performance applications, supporting multiple simulta- Supports up to 8 NT endpoints per switch, each endpoint can neous peer-to-peer traffic flows. Target applications include multi-host or communicate with other switch partitions or external PCIe intelligent I/O based systems where inter-domain communication is domains or CPUs required, such as servers, storage, communications, and embedded 6 BARs per NT Endpoint systems. Bar address translation Features All BARs support 32/64-bit base and limit address translation High Performance Non-Blocking Switch Architecture Two BARs (BAR2 and BAR4) support look-up table based 32-lane, 24-port PCIe switch with flexible port configuration address translation Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s 32 inbound and outbound doorbell registers Gen1 operation 4 inbound and outbound message registers Delivers up to 32 GBps (256 Gbps) of switching capacity Supports up to 64 masters Supports 128 Bytes to 2 KB maximum payload size Unlimited number of outstanding transactions Low latency cut-through architecture Multicast Supports one virtual channel and eight traffic classes Compliant with the PCI-SIG multicast Port Configurability Supports 64 multicast groups Four x8 stacks Supports multicast across non-transparent port Two x8 stacks, each configurable as: Multicast overlay mechanism support One x8 port ECRC regeneration support Two x4 ports Integrated Direct Memory Access (DMA) Controllers Four x2 ports Supports up to 2 DMA upstream ports, each with 2 DMA chan- Eight x1 ports nels Several combinations of the above lane widths Supports 32-bit and 64-bit memory-to-memory transfers Two x8 stacks, each configurable as: Fly-by translation provides reduced latency and increased One x8 port performance over buffered approach Two x4 ports Supports arbitrary source and destination address alignment Four x2 ports Supports intra- as well as inter-partition data transfers using Several combinations of the above lane widths the non-transparent endpoint Automatic per port link width negotiation Supports DMA transfers to multicast groups (x8 x4 x2 x1) Linked list descriptor-based operation Crosslink support Flexible addressing modes Automatic lane reversal Linear addressing Per lane SerDes configuration Constant addressing De-emphasis Quality of Service (QoS) Receive equalization Port arbitration Drive strength Round robin Innovative Switch Partitioning Feature Request metering Supports up to 8 fully independent switch partitions IDT proprietary feature that balances bandwidth among Logically independent switches in the same device switch ports for maximum system throughput Configurable downstream port device numbering Supports dynamic reconfiguration of switch partitions IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 37 December 17, 2013 2013 Integrated Device Technology, IncIDT 89HPES32NT24BG2 Datasheet High performance switch core architecture 9 General Purpose I/O Combined Input Output Queued (CIOQ) switch architecture Test and Debug with large buffers Ability to inject AER errors simplifies in system error handling Clocking software validation Supports 100 MHz and 125 MHz reference clock frequencies On-chip link activity and status outputs available for several ports Flexible port clocking modes Common clock Per port link activity and status outputs available using 2 external I C I/O expander for all remaining ports Non-common clock Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG Local port clock with SSC (spread spectrum setting) and port reference clock input Standards and Compatibility Hot-Plug and Hot Swap PCI Express Base Specification 2.1 compliant Hot-plug controller on all ports Implements the following optional PCI Express features Hot-plug supported on all downstream switch ports Advanced Error Reporting (AER) on all ports 2 All ports support hot-plug using low-cost external I C I/O End-to-End CRC (ECRC) expanders Access Control Services (ACS) Configurable presence-detect supports card and cable appli- Device Serial Number Enhanced Capability cations Sub-System ID and Sub-System Vendor ID Capability GPE output pin for hot-plug event notification Internal Error Reporting Enables SCI/SMI generation for legacy operating system Multicast support VGA and ISA enable Hot-swap capable I/O L0s and L1 ASPM Power Management ARI Supports D0, D3hot and D3 power management states Power Supplies Active State Power Management (ASPM) Requires three power supply voltages (1.0V, 2.5V, and 3.3V) Supports L0, L0s, L1, L2/L3 Ready, and L3 link states Packaged in a 23mm x 23mm 484-ball Flip Chip BGA with Configurable L0s and L1 entry timers allow performance/ 1mm ball spacing power-savings tuning SerDes power savings Product Description Supports low swing / half-swing SerDes operation With Non-Transparent Bridging functionality and innovative Switch SerDes associated with unused ports are turned off Partitioning feature, the PES32NT24BG2 allows true multi-host or multi- SerDes associated with unused lanes are placed in a low processor communications in a single device. Integrated DMA control- power state lers enable high-performance system design by off-loading data transfer Reliability, Availability, and Serviceability (RAS) operations across memories from the processors. Each lane is capable ECRC support of 5 GT/s link speed in both directions and is fully compliant with PCI AER on all ports Express Base Specification 2.1. SECDED ECC protection on all internal RAMs A non-transparent bridge (NTB) is required when two PCI Express End-to-end data path parity protection domains need to communicate to each other. The main function of the Checksum Serial EEPROM content protected NTB block is to initialize and translate addresses and device IDs to Ability to generate an interrupt (INTx or MSI) on link up/down allow data exchange across PCI Express domains. The major function- transitions alities of the NTB block are summarized in Table 1. Initialization / Configuration Supports Root (BIOS, OS, or driver), Serial EEPROM, or SMBus switch initialization Common switch configurations are supported with pin strap- ping (no external components) Supports in-system Serial EEPROM initialization/program- ming On-Die Temperature Sensor Range of 0 to 127.5 degrees Celsius Three programmable temperature thresholds with over and under temperature threshold alarms Automatic recording of maximum high or minimum low temperature 2 of 37 December 17, 2013