89HPES32T8G2 32-Lane 8-Port PCIe Gen2 Data Sheet I/O Expansion Switch Drive strength Device Overview Initialization / Configuration The 89HPES32T8G2 is a member of the IDT PRECISE family of PCI Express switching solutions. The PES32T8G2 is a 32-lane, 8-port Supports Root (BIOS, OS, or driver), Serial EEPROM, or switch optimized for PCI Express Gen2 packet switching in high-perfor- SMBus switch initialization mance applications. Target applications include servers, storage, Common switch configurations are supported with pin strap- communications, embedded systems, and multi-host or intelligent I/O ping (no external components) based systems with inter-domain communication. Supports in-system Serial EEPROM initialization/program- ming Features High Performance Non-Blocking Switch Architecture Quality of Service (QoS) 32-lane 8-port PCIe switch Port arbitration Four x8 switch ports each of which can bifurcate to two x4 Round robin ports (total of eight x4 ports) Request metering Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s IDT proprietary feature that balances bandwidth among Gen1 operation switch ports for maximum system throughput Delivers up to 32 GBps (256 Gbps) of switching capacity High performance switch core architecture Supports 128 Bytes to 2 KB maximum payload size Combined Input Output Queued (CIOQ) switch architecture Low latency cut-through architecture with large buffers Supports one virtual channel and eight traffic classes Multicast Standards and Compatibility Compliant to the PCI-SIG multicast ECN Supports arbitrary multicasting of Posted transactions PCI Express Base Specification 2.0 compliant Supports 64 multicast groups Implements the following optional PCI Express features Multicast overlay mechanism support Advanced Error Reporting (AER) on all ports ECRC regeneration support End-to-End CRC (ECRC) Clocking Access Control Services (ACS) Supports 100 MHz and 125 MHz reference clock frequencies Power Budgeting Enhanced Capability Flexible clocking modes Device Serial Number Enhanced Capability Common clock Sub-System ID and Sub-System Vendor ID Capability Non-common clock Internal Error Reporting ECN Hot-Plug and Hot Swap Multicast ECN Hot-plug controller on all ports VGA and ISA enable Hot-plug supported on all downstream switch ports L0s and L1 ASPM 2 All ports support hot-plug using low-cost external I C I/O ARI ECN expanders Port Configurability Configurable presence detect supports card and cable appli- x4 and x8 ports cations Ability to merge adjacent x4 ports to create a x8 port GPE output pin for hot-plug event notification Automatic per port link width negotiation Enables SCI/SMI generation for legacy operating system (x8 x4 x2 x1) support Crosslink support Hot-swap capable I/O Automatic lane reversal Power Management Autonomous and software managed link width and speed Supports D0, D3hot and D3 power management states control Active State Power Management (ASPM) Per lane SerDes configuration Supports L0, L0s, L1, L2/L3 Ready and L3 link states De-emphasis Configurable L0s and L1 entry timers allow performance/ Receive equalization power-savings tuning IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 39 November 28, 2011IDT 89HPES32T8G2 Data Sheet Supports PCI Express Power Budgeting Capability Product Description SerDes power savings Utilizing standard PCI Express interconnect, the PES32T8G2 Supports low swing / half-swing SerDes operation provides the most efficient fan-out solution for applications requiring SerDes optionally turned-off in D3hot high throughput, low latency, and simple board layout with a minimum number of board layers. It provides 32 GBps (256 Gbps) of aggregated, SerDes associated with unused ports are turned-off full-duplex switching capacity through 32 integrated serial lanes, using SerDes associated with unused lanes are placed in a low proven and robust IDT technology. Each lane provides 5 GT/s of band- power state width in both directions and is fully compliant with PCI Express Base 9 General Purpose I/O Specification, Revision 2.0. Reliability, Availability and Serviceability (RAS) The PES32T8G2 is based on a flexible and efficient layered archi- ECRC support tecture. The PCI Express layer consists of SerDes, Physical, Data Link AER on all ports and Transaction layers in compliance with PCI Express Base specifica- SECDED ECC protection on all internal RAMs tion Revision 2.0. The PES32T8G2 can operate either as a store and End-to-end data path parity protection forward or cut-through switch. It supports eight Traffic Classes (TCs) Checksum Serial EEPROM content protected and one Virtual Channel (VC) with sophisticated resource management Autonomous link reliability (preserves system operation in the to enable efficient switching and I/O connectivity for servers, storage, presence of faulty links) and embedded processors with limited connectivity. Ability to generate an interrupt (INTx or MSI) on link up/down transitions Test and Debug On-chip link activity and status outputs available for Port 0 (upstream port) Per port link activity and status outputs available using 2 external I C I/O expander for all other ports SerDes test modes Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG Power Supplies Requires only two power supply voltages (1.0 V and 2.5 V) Note that a 3.3V is preferred for V I/O DD No power sequencing requirements Packaged in a 23mm x 23mm 484-ball Flip Chip BGA with 1mm ball spacing 2 of 39 November 28, 2011