89HPES48H12G2 48-Lane 12-Port PCIe Gen2 Data Sheet System Interconnect Switch De-emphasis Device Overview Receive equalization The 89HPES48H12G2 is a member of the IDT PRECISE family of PCI Express switching solutions. The PES48H12G2 is a 48-lane, 12- Drive strength port system interconnect switch optimized for PCI Express Gen2 packet Switch Partitioning switching in high-performance applications, supporting multiple simulta- IDT proprietary feature that creates logically independent neous peer-to-peer traffic flows. Target applications include servers, switches in the device storage, communications, embedded systems, and multi-host or intelli- Supports up to 12 fully independent switch partitions gent I/O based systems with inter-domain communication. Configurable downstream port device numbering Supports dynamic reconfiguration of switch partitions Features High Performance Non-Blocking Switch Architecture Dynamic port reconfiguration downstream, upstream 48-lane 12-port PCIe switch Dynamic migration of ports between partitions Six x8 ports switch ports each of which can bifurcate to two Movable upstream port within and between switch partitions x4 ports (total of twelve x4 ports) Initialization / Configuration Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s Supports Root (BIOS, OS, or driver), Serial EEPROM, or Gen1 operation SMBus switch initialization Delivers up to 48 GBps (384 Gbps) of switching capacity Common switch configurations are supported with pin strap- Supports 128 Bytes to 2 KB maximum payload size ping (no external components) Low latency cut-through architecture Supports in-system Serial EEPROM initialization/program- ming Supports one virtual channel and eight traffic classes Quality of Service (QoS) Standards and Compatibility Port arbitration PCI Express Base Specification 2.0 compliant Round robin Implements the following optional PCI Express features Request metering Advanced Error Reporting (AER) on all ports IDT proprietary feature that balances bandwidth among End-to-End CRC (ECRC) switch ports for maximum system throughput Access Control Services (ACS) High performance switch core architecture Power Budgeting Enhanced Capability Combined Input Output Queued (CIOQ) switch architecture Device Serial Number Enhanced Capability with large buffers Sub-System ID and Sub-System Vendor ID Capability Multicast Internal Error Reporting ECN Compliant to the PCI-SIG multicast ECN Multicast ECN Supports arbitrary multicasting of Posted transactions VGA and ISA enable Supports 64 multicast groups L0s and L1 ASPM Multicast overlay mechanism support ECRC regeneration support ARI ECN Clocking Port Configurability Supports 100 MHz and 125 MHz reference clock frequencies x4 and x8 ports Flexible clocking modes Ability to merge adjacent x4 ports to create a x8 port Common clock Automatic per port link width negotiation Non-common clock (x8 x4 x2 x1) Local port clock with SSC and port reference clock input Crosslink support Hot-Plug and Hot Swap Automatic lane reversal Hot-plug controller on all ports Autonomous and software managed link width and speed control Hot-plug supported on all downstream switch ports Per lane SerDes configuration IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 44 November 28, 2011IDT 89HPES48H12G2 Data Sheet 2 All ports support hot-plug using low-cost external I C I/O Product Description expanders Utilizing standard PCI Express Gen2 interconnect, the Configurable presence detect supports card and cable appli- PES48H12G2 provides the most efficient system interconnect switching cations solution for applications requiring high throughput, low latency, and GPE output pin for hot-plug event notification simple board layout with a minimum number of board layers. It provides Enables SCI/SMI generation for legacy operating system 48 GBps (384 Gbps) of aggregated, full-duplex switching capacity support through 48 integrated serial lanes, using proven and robust IDT tech- Hot swap capable I/O nology. Each lane is capable of 5 GT/s of bandwidth in both directions and is fully compliant with PCI Express Base specification 2.0. Power Management Supports D0, D3hot and D3 power management states The PES48H12G2 is based on a flexible and efficient layered archi- tecture. The PCI Express layer consists of SerDes, Physical, Data Link Active State Power Management (ASPM) and Transaction layers in compliance with PCI Express Base specifica- Supports L0, L0s, L1, L2/L3 Ready and L3 link states tion Revision 2.0. The PES48H12G2 can operate either as a store and Configurable L0s and L1 entry timers allow performance/ forward or cut-through switch. It supports eight Traffic Classes (TCs) power-savings tuning and one Virtual Channel (VC) with sophisticated resource management Supports PCI Express Power Budgeting Capability to enable efficient switching and I/O connectivity for servers, storage, SerDes power savings and embedded processors with limited connectivity. Supports low swing / half-swing SerDes operation The PES48H12G2 is a partitionable PCIe switch. This means that in SerDes optionally turned-off in D3hot addition to operating as a standard PCI express switch, the SerDes associated with unused ports are turned-off PES48H12G2 ports may be partitioned into groups that logically SerDes associated with unused lanes are placed in a low operate as completely independent PCIe switches. Figure 2 illustrates a power state three partition PES48H12G2 configuration. 9 General Purpose I/O Reliability, Availability and Serviceability (RAS) ECRC support AER on all ports SECDED ECC protection on all internal RAMs End-to-end data path parity protection Checksum Serial EEPROM content protected Autonomous link reliability (preserves system operation in the presence of faulty links) Ability to generate an interrupt (INTx or MSI) on link up/down transitions Test and Debug On-chip link activity and status outputs available for Port 0 (upstream port) Per port link activity and status outputs available using 2 external I C I/O expander for all other ports SerDes test modes Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG Power Supplies Requires only two power supply voltages (1.0 V and 2.5 V) Note that a 3.3V is preferred for V I/O DD No power sequencing requirements Packaged in a 27mm x 27mm 676-ball Flip Chip BGA with 1mm ball spacing 2 of 44 November 28, 2011