89HPES64H16G2 64-Lane 16-Port PCIe Gen2 Data Sheet System Interconnect Switch Per lane SerDes configuration Device Overview De-emphasis The 89HPES64H16G2 is a member of the IDT PRECISE family of PCI Express switching solutions. The PES64H16G2 is a 64-lane, 16- Receive equalization port system interconnect switch optimized for PCI Express Gen2 packet Drive strength switching in high-performance applications, supporting multiple simulta- Switch Partitioning neous peer-to-peer traffic flows. Target applications include servers, IDT proprietary feature that creates logically independent storage, communications, embedded systems, and multi-host or intelli- switches in the device gent I/O based systems with inter-domain communication. Supports up to 16 fully independent switch partitions Configurable downstream port device numbering Features High Performance Non-Blocking Switch Architecture Supports dynamic reconfiguration of switch partitions 64-lane 16-port PCIe switch Dynamic port reconfiguration downstream, upstream Eight x8 ports switch ports each of which can bifurcate to two Dynamic migration of ports between partitions x4 ports (total of sixteen x4 ports) Movable upstream port within and between switch partitions Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s Initialization / Configuration Gen1 operation Supports Root (BIOS, OS, or driver), Serial EEPROM, or Delivers up to 64 GBps (512 Gbps) of switching capacity SMBus switch initialization Supports 128 Bytes to 2 KB maximum payload size Common switch configurations are supported with pin strap- ping (no external components) Low latency cut-through architecture Supports in-system Serial EEPROM initialization/program- Supports one virtual channel and eight traffic classes ming Standards and Compatibility Quality of Service (QoS) PCI Express Base Specification 2.0 compliant Port arbitration Implements the following optional PCI Express features Round robin Advanced Error Reporting (AER) on all ports Request metering End-to-End CRC (ECRC) IDT proprietary feature that balances bandwidth among Access Control Services (ACS) switch ports for maximum system throughput Power Budgeting Enhanced Capability High performance switch core architecture Device Serial Number Enhanced Capability Combined Input Output Queued (CIOQ) switch architecture Sub-System ID and Sub-System Vendor ID Capability with large buffers Internal Error Reporting ECN Multicast Multicast ECN Compliant to the PCI-SIG multicast ECN VGA and ISA enable Supports arbitrary multicasting of Posted transactions L0s and L1 ASPM Supports 64 multicast groups ARI ECN Independent multicast support within each switch partition Compatible with IDT 89HPES64H16 PCIe Gen1 switch Clocking Port Configurability Supports 100 MHz and 125 MHz reference clock frequencies x4 and x8 ports Flexible clocking modes Ability to merge adjacent x4 ports to create a x8 port Common clock Automatic per port link width negotiation Non-common clock (x8 x4 x2 x1) Hot-Plug and Hot Swap Crosslink support Hot-plug controller on all ports Automatic lane reversal Hot-plug supported on all downstream switch ports Autonomous and software managed link width and speed control IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 57 November 28, 2011IDT 89HPES64H16G2 Data Sheet 2 All ports support hot-plug using low-cost external I C I/O Product Description expanders Utilizing standard PCI Express interconnect, the PES64H16G2 Configurable presence detect supports card and cable appli- provides the most efficient fan-out solution for applications requiring cations high throughput, low latency, and simple board layout with a minimum GPE output pin for hot-plug event notification number of board layers. It provides 64 GBps (512 Gbps) of aggregated, Enables SCI/SMI generation for legacy operating system full-duplex switching capacity through 64 integrated serial lanes, using support proven and robust IDT technology. Each lane provides 5 GT/s of band- Hot-swap capable I/O width in both directions and is fully compliant with PCI Express Base Specification, Revision 2.0. Power Management Supports D0, D3hot and D3 power management states The PES64H16G2 is based on a flexible and efficient layered archi- tecture. The PCI Express layer consists of SerDes, Physical, Data Link Active State Power Management (ASPM) and Transaction layers in compliance with PCI Express Base specifica- Supports L0, L0s, L1, L2/L3 Ready and L3 link states tion Revision 2.0. The PES64H16G2 can operate either as a store and Configurable L0s and L1 entry timers allow performance/ forward or cut-through switch. It supports eight Traffic Classes (TCs) power-savings tuning and one Virtual Channel (VC) with sophisticated resource management Supports PCI Express Power Budgeting Capability to enable efficient switching and I/O connectivity for servers, storage, SerDes power savings and embedded processors with limited connectivity. Supports low swing / half-swing SerDes operation The PES64H16G2 is a partitionable PCIe switch. This means that in SerDes optionally turned-off in D3hot addition to operating as a standard PCI express switch, the SerDes associated with unused ports are turned-off PES64H16G2 ports may be partitioned into groups that logically SerDes associated with unused lanes are placed in a low operate as completely independent PCIe switches. Figure 2 illustrates a power state three partition PES64H16G2 configuration. 32 General Purpose I/O Reliability, Availability and Serviceability (RAS) ECRC support AER on all ports SECDED ECC protection on all internal RAMs End-to-end data path parity protection Checksum Serial EEPROM content protected Autonomous link reliability (preserves system operation in the presence of faulty links) Ability to generate an interrupt (INTx or MSI) on link up/down transitions Test and Debug On-chip link activity and status outputs available for Port 0 (upstream port) Per port link activity and status outputs available using 2 external I C I/O expander for all other ports SerDes test modes Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG Power Supplies Requires only two power supply voltages (1.0 V and 2.5 V) Note that a 3.3V is preferred for V I/O DD No power sequencing requirements Packaged in a 35mm x 35mm 1156-ball Flip Chip BGA with 1mm ball spacing Compatible with IDT 89HPES64H16 PCIe Gen1 switch Note: For pin compatibility issues, contact the IDT help desk at ssdhelp idt.com. 2 of 57 November 28, 2011