89HPES12NT12G2 12-Lane 12-Port PCIe Gen2 Datasheet System Interconnect Switch Non-Transparent Bridging (NTB) Support Device Overview Supports up to 3 NT endpoints per switch, each endpoint can The 89HPES12NT12G2 is a member of the IDT family of PCI communicate with other switch partitions or external PCIe Express switching solutions. The PES12NT12G2 is a 12-lane, 12-port domains or CPUs system interconnect switch optimized for PCI Express Gen2 packet 6 BARs per NT Endpoint switching in high-performance applications, supporting multiple simulta- Bar address translation neous peer-to-peer traffic flows. Target applications include multi-host or All BARs support 32/64-bit base and limit address translation intelligent I/O based systems where inter-domain communication is Two BARs (BAR2 and BAR4) support look-up table based required, such as servers, storage, communications, and embedded address translation systems. 32 inbound and outbound doorbell registers Features 4 inbound and outbound message registers High Performance Non-Blocking Switch Architecture Supports up to 64 masters 12-lane, 12-port PCIe switch with flexible port configuration Unlimited number of outstanding transactions Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s Multicast Gen1 operation Compliant with the PCI-SIG multicast Delivers up to 12 GBps (96 Gbps) of switching capacity Supports 64 multicast groups Supports 128 Bytes to 2 KB maximum payload size Supports multicast across non-transparent port Low latency cut-through architecture Multicast overlay mechanism support Supports one virtual channel and eight traffic classes ECRC regeneration support Port Configurability Integrated Direct Memory Access (DMA) Controllers Twelve x1 ports configurable as follows: Supports up to 2 DMA upstream ports, each with 2 DMA chan- One x4 stack nels Four x1 ports (ports 0 through 3 are not capable of Supports 32-bit and 64-bit memory-to-memory transfers merging with an adjacent port) Fly-by translation provides reduced latency and increased Two x4 stacks configurable as: performance over buffered approach Two x4 ports Supports arbitrary source and destination address alignment Four x2 ports Supports intra- as well as inter-partition data transfers using Eight x1 ports the non-transparent endpoint Automatic per port link width negotiation Supports DMA transfers to multicast groups (x4 x2 x1) Linked list descriptor-based operation Crosslink support Flexible addressing modes Automatic lane reversal Linear addressing Per lane SerDes configuration Constant addressing De-emphasis Quality of Service (QoS) Receive equalization Port arbitration Drive strength Round robin Innovative Switch Partitioning Feature Request metering Supports up to 4 fully independent switch partitions IDT proprietary feature that balances bandwidth among Logically independent switches in the same device switch ports for maximum system throughput Configurable downstream port device numbering High performance switch core architecture Supports dynamic reconfiguration of switch partitions Combined Input Output Queued (CIOQ) switch architecture Dynamic port reconfiguration downstream, upstream, with large buffers non-transparent bridge Clocking Dynamic migration of ports between partitions Supports 100 MHz and 125 MHz reference clock frequencies Movable upstream port within and between switch partitions Flexible port clocking modes IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 32 December 16, 2013IDT 89HPES12NT12G2 Datasheet Common clock 9 General Purpose I/O Non-common clock Test and Debug Local port clock with SSC (spread spectrum setting) and port Ability to inject AER errors simplifies in system error handling reference clock input software validation Hot-Plug and Hot Swap On-chip link activity and status outputs available for several Hot-plug controller on all ports ports Hot-plug supported on all downstream switch ports Per port link activity and status outputs available using 2 2 external I C I/O expander for all remaining ports All ports support hot-plug using low-cost external I C I/O expanders Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG Configurable presence-detect supports card and cable appli- Standards and Compatibility cations PCI Express Base Specification 2.1 compliant GPE output pin for hot-plug event notification Implements the following optional PCI Express features Enables SCI/SMI generation for legacy operating system Advanced Error Reporting (AER) on all ports support End-to-End CRC (ECRC) Hot-swap capable I/O Access Control Services (ACS) Power Management Device Serial Number Enhanced Capability Supports D0, D3hot and D3 power management states Sub-System ID and Sub-System Vendor ID Capability Active State Power Management (ASPM) Internal Error Reporting Supports L0, L0s, L1, L2/L3 Ready, and L3 link states Multicast Configurable L0s and L1 entry timers allow performance/ VGA and ISA enable power-savings tuning L0s and L1 ASPM SerDes power savings ARI Supports low swing / half-swing SerDes operation Power Supplies SerDes associated with unused ports are turned off Requires three power supply voltages (1.0V, 2.5V, and 3.3V) SerDes associated with unused lanes are placed in a low Packaged in a 19mm x 19mm 324-ball Flip Chip BGA with power state 1mm ball spacing Reliability, Availability, and Serviceability (RAS) ECRC support Product Description AER on all ports With Non-Transparent Bridging functionality and innovative Switch SECDED ECC protection on all internal RAMs Partitioning feature, the PES12NT12G2 allows true multi-host or multi- End-to-end data path parity protection processor communications in a single device. Integrated DMA control- Checksum Serial EEPROM content protected lers enable high-performance system design by off-loading data transfer Ability to generate an interrupt (INTx or MSI) on link up/down operations across memories from the processors. Each lane is capable transitions of 5 GT/s link speed in both directions and is fully compliant with PCI Initialization / Configuration Express Base Specification 2.1. Supports Root (BIOS, OS, or driver), Serial EEPROM, or A non-transparent bridge (NTB) is required when two PCI Express SMBus switch initialization domains need to communicate to each other. The main function of the Common switch configurations are supported with pin strap- NTB block is to initialize and translate addresses and device IDs to ping (no external components) allow data exchange across PCI Express domains. The major function- Supports in-system Serial EEPROM initialization/program- alities of the NTB block are summarized in Table 1. ming On-Die Temperature Sensor Range of 0 to 127.5 degrees Celsius Three programmable temperature thresholds with over and under temperature threshold alarms Automatic recording of maximum high or minimum low temperature 2 of 32 December 16, 2013