89HPES16NT16G2 16-Lane 16-Port PCIe Gen2 Datasheet System Interconnect Switch Dynamic port reconfiguration downstream, upstream, Device Overview non-transparent bridge The 89HPES16NT16G2 is a member of the IDT family of PCI Dynamic migration of ports between partitions Express switching solutions. The PES16NT16G2 is a 16-lane, 16-port Movable upstream port within and between switch partitions system interconnect switch optimized for PCI Express Gen2 packet Non-Transparent Bridging (NTB) Support switching in high-performance applications, supporting multiple simulta- Supports up to 4 NT endpoints per switch, each endpoint can neous peer-to-peer traffic flows. Target applications include multi-host or communicate with other switch partitions or external PCIe intelligent I/O based systems where inter-domain communication is domains or CPUs required, such as servers, storage, communications, and embedded 6 BARs per NT Endpoint systems. Bar address translation All BARs support 32/64-bit base and limit address translation Features High Performance Non-Blocking Switch Architecture Two BARs (BAR2 and BAR4) support look-up table based 16-lane, 16-port PCIe switch with flexible port configuration address translation Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s 32 inbound and outbound doorbell registers Gen1 operation 4 inbound and outbound message registers Delivers up to 16 GBps (128 Gbps) of switching capacity Supports up to 64 masters Supports 128 Bytes to 2 KB maximum payload size Unlimited number of outstanding transactions Low latency cut-through architecture Multicast Supports one virtual channel and eight traffic classes Compliant with the PCI-SIG multicast Port Configurability Supports 64 multicast groups Three stacks Supports multicast across non-transparent port One x8 port configurable as: Multicast overlay mechanism support One x8 port ECRC regeneration support Two x4 ports Integrated Direct Memory Access (DMA) Controllers Four x2 ports Supports up to 2 DMA upstream ports, each with 2 DMA chan- Eight x1 ports nels Several combinations of the above lane widths Supports 32-bit and 64-bit memory-to-memory transfers One x4 port configurable as: Fly-by translation provides reduced latency and increased One x4 port performance over buffered approach Two x2 ports Supports arbitrary source and destination address alignment 4 x1 ports Supports intra- as well as inter-partition data transfers using Four x1 ports the non-transparent endpoint Automatic per port link width negotiation Supports DMA transfers to multicast groups (x8 x4 x2 x1) Linked list descriptor-based operation Crosslink support Flexible addressing modes Automatic lane reversal Linear addressing Per lane SerDes configuration Constant addressing De-emphasis Quality of Service (QoS) Receive equalization Port arbitration Drive strength Round robin Innovative Switch Partitioning Feature Request metering Supports up to 4 fully independent switch partitions IDT proprietary feature that balances bandwidth among switch ports for maximum system throughput Logically independent switches in the same device High performance switch core architecture Configurable downstream port device numbering Combined Input Output Queued (CIOQ) switch architecture Supports dynamic reconfiguration of switch partitions with large buffers IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 33 December 17, 2013IDT 89HPES16NT16G2 Datasheet Clocking 9 General Purpose I/O Supports 100 MHz and 125 MHz reference clock frequencies Test and Debug Flexible port clocking modes Ability to inject AER errors simplifies in system error handling software validation Common clock On-chip link activity and status outputs available for several Non-common clock ports Local port clock with SSC (spread spectrum setting) and port Per port link activity and status outputs available using reference clock input 2 external I C I/O expander for all remaining ports Hot-Plug and Hot Swap Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG Hot-plug controller on all ports Standards and Compatibility Hot-plug supported on all downstream switch ports 2 PCI Express Base Specification 2.1 compliant All ports support hot-plug using low-cost external I C I/O expanders Implements the following optional PCI Express features Configurable presence-detect supports card and cable appli- Advanced Error Reporting (AER) on all ports cations End-to-End CRC (ECRC) GPE output pin for hot-plug event notification Access Control Services (ACS) Enables SCI/SMI generation for legacy operating system Device Serial Number Enhanced Capability support Sub-System ID and Sub-System Vendor ID Capability Hot-swap capable I/O Internal Error Reporting Power Management Multicast Supports D0, D3hot and D3 power management states VGA and ISA enable Active State Power Management (ASPM) L0s and L1 ASPM Supports L0, L0s, L1, L2/L3 Ready, and L3 link states ARI Configurable L0s and L1 entry timers allow performance/ Power Supplies power-savings tuning Requires three power supply voltages (1.0V, 2.5V, and 3.3V) SerDes power savings Packaged in a 19mm x 19mm 324-ball Flip Chip BGA with Supports low swing / half-swing SerDes operation 1mm ball spacing SerDes associated with unused ports are turned off Product Description SerDes associated with unused lanes are placed in a low power state With Non-Transparent Bridging functionality and innovative Switch Reliability, Availability, and Serviceability (RAS) Partitioning feature, the PES16NT16G2 allows true multi-host or multi- ECRC support processor communications in a single device. Integrated DMA control- AER on all ports lers enable high-performance system design by off-loading data transfer operations across memories from the processors. Each lane is capable SECDED ECC protection on all internal RAMs of 5 GT/s link speed in both directions and is fully compliant with PCI End-to-end data path parity protection Express Base Specification 2.1. Checksum Serial EEPROM content protected Ability to generate an interrupt (INTx or MSI) on link up/down A non-transparent bridge (NTB) is required when two PCI Express transitions domains need to communicate to each other. The main function of the Initialization / Configuration NTB block is to initialize and translate addresses and device IDs to allow data exchange across PCI Express domains. The major function- Supports Root (BIOS, OS, or driver), Serial EEPROM, or SMBus switch initialization alities of the NTB block are summarized in Table 1. Common switch configurations are supported with pin strap- ping (no external components) Supports in-system Serial EEPROM initialization/program- ming On-Die Temperature Sensor Range of 0 to 127.5 degrees Celsius Three programmable temperature thresholds with over and under temperature threshold alarms Automatic recording of maximum high or minimum low temperature 2 of 33 December 17, 2013