89HPES64H16AG2 64-Lane 16-Port PCIe Gen2 Data Sheet System Interconnect Switch De-emphasis Device Overview Receive equalization The 89HPES64H16AG2 is a member of the IDT PRECISE family of PCI Express switching solutions. The PES64H16AG2 is a 64-lane, Drive strength 16-port system interconnect switch optimized for PCI Express Gen2 Switch Partitioning packet switching in high-performance applications, supporting multiple IDT proprietary feature that creates logically independent simultaneous peer-to-peer traffic flows. Target applications include switches in the device servers, storage, communications, embedded systems, and multi-host Supports up to 16 fully independent switch partitions or intelligent I/O based systems with inter-domain communication. Configurable downstream port device numbering Supports dynamic reconfiguration of switch partitions Features High Performance Non-Blocking Switch Architecture Dynamic port reconfiguration downstream, upstream 64-lane 16-port PCIe switch Dynamic migration of ports between partitions Eight x8 switch ports each of which can bifurcate to two x4 Movable upstream port within and between switch partitions ports (total of sixteen x4 ports) Initialization / Configuration Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s Supports Root (BIOS, OS, or driver), Serial EEPROM, or Gen1 operation SMBus switch initialization Delivers up to 64 GBps (512 Gbps) of switching capacity Common switch configurations are supported with pin strap- Supports 128 Bytes to 2 KB maximum payload size ping (no external components) Low latency cut-through architecture Supports in-system Serial EEPROM initialization/program- ming Supports one virtual channel and eight traffic classes Quality of Service (QoS) Standards and Compatibility Port arbitration PCI Express Base Specification 2.0 compliant Round robin Implements the following optional PCI Express features Request metering Advanced Error Reporting (AER) on all ports IDT proprietary feature that balances bandwidth among End-to-End CRC (ECRC) switch ports for maximum system throughput Access Control Services (ACS) High performance switch core architecture Power Budgeting Enhanced Capability Combined Input Output Queued (CIOQ) switch architecture Device Serial Number Enhanced Capability with large buffers Sub-System ID and Sub-System Vendor ID Capability Multicast Internal Error Reporting ECN Compliant to the PCI-SIG multicast ECN Multicast ECN Supports arbitrary multicasting of Posted transactions VGA and ISA enable Supports 64 multicast groups L0s and L1 ASPM Multicast overlay mechanism support ECRC regeneration support ARI ECN Clocking Port Configurability Supports 100 MHz and 125 MHz reference clock frequencies x4 and x8 ports Flexible port clocking modes Ability to merge adjacent x4 ports to create a x8 port Common clock Automatic per port link width negotiation Non-common clock (x8 x4 x2 x1) Local port clock with SSC and port reference clock input Crosslink support Hot-Plug and Hot Swap Automatic lane reversal Hot-plug controller on all ports Autonomous and software managed link width and speed control Hot-plug supported on all downstream switch ports Per lane SerDes configuration All ports support hot-plug using low-cost external I2C I/O expanders IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 62 November 28, 2011IDT 89HPES64H16AG2 Data Sheet Direct package pin support for hot-plug on 5 ports Product Description Configurable presence detect supports card and cable appli- Utilizing standard PCI Express interconnect, the PES64H16AG2 cations provides the most efficient fan-out solution for applications requiring GPE output pin for hot-plug event notification high throughput, low latency, and simple board layout with a minimum Enables SCI/SMI generation for legacy operating system number of board layers. It provides 64 GBps (512 Gbps) of aggregated, support full-duplex switching capacity through 64 integrated serial lanes, using proven and robust IDT technology. Each lane provides 5 GT/s of band- Hot-swap capable I/O width in both directions and is fully compliant with PCI Express Base Power Management Specification, Revision 2.0. Supports D0, D3hot and D3 power management states The PES64H16AG2 is based on a flexible and efficient layered Active State Power Management (ASPM) architecture. The PCI Express layer consists of SerDes, Physical, Data Supports L0, L0s, L1, L2/L3 Ready and L3 link states Link and Transaction layers in compliance with PCI Express Base spec- Configurable L0s and L1 entry timers allow performance/ ification Revision 2.0. The PES64H16AG2 can operate either as a store power-savings tuning and forward or cut-through switch. It supports eight Traffic Classes Supports PCI Express Power Budgeting Capability (TCs) and one Virtual Channel (VC) with sophisticated resource SerDes power savings management to enable efficient switching and I/O connectivity for Supports low swing / half-swing SerDes operation servers, storage, and embedded processors with limited connectivity. SerDes optionally turned-off in D3hot The PES64H16AG2 is a partitionable PCIe switch. This means that SerDes associated with unused ports are turned-off in addition to operating as a standard PCI express switch, the SerDes associated with unused lanes are placed in a low PES64H16AG2 ports may be partitioned into groups that logically power state operate as completely independent PCIe switches. Figure 2 illustrates a 54 General Purpose I/O three partition PES64H16AG2 configuration. Reliability, Availability and Serviceability (RAS) ECRC support AER on all ports SECDED ECC protection on all internal RAMs End-to-end data path parity protection Checksum Serial EEPROM content protected Autonomous link reliability (preserves system operation in the presence of faulty links) Ability to generate an interrupt (INTx or MSI) on link up/down transitions Test and Debug On-chip link activity and status outputs available for several ports including the upstream ports Per port link activity and status outputs available using 2 external I C I/O expander for all remaining ports SerDes test modes Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG Power Supplies Requires only two power supply voltages (1.0 V and 2.5 V) Note that a 3.3V is preferred for V I/O DD No power sequencing requirements Packaged in a 35mm x 35mm 1156-ball Flip Chip BGA with 1mm ball spacing 2 of 62 November 28, 2011