89HPES48H12AG2 48-Lane 12-Port PCIe Gen2 Datasheet System Interconnect Switch De-emphasis Device Overview Receive equalization The 89HPES48H12AG2 is a member of the IDT PRECISE family Drive strength of PCI Express switching solutions. The PES48H12AG2 is a 48-lane, 12-port system interconnect switch optimized for PCI Express Gen2 Switch Partitioning packet switching in high-performance applications, supporting multiple IDT proprietary feature that creates logically independent simultaneous peer-to-peer traffic flows. Target applications include switches in the device servers, storage, communications, embedded systems, and multi-host Supports up to 12 fully independent switch partitions or intelligent I/O based systems with inter-domain communication. Configurable downstream port device numbering Supports dynamic reconfiguration of switch partitions Features High Performance Non-Blocking Switch Architecture Dynamic port reconfiguration downstream, upstream Dynamic migration of ports between partitions 48-lane 12-port PCIe switch Movable upstream port within and between switch partitions Six x8 ports switch ports each of which can bifurcate to two x4 ports (total of twelve x4 ports) Initialization / Configuration Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s Supports Root (BIOS, OS, or driver), Serial EEPROM, or Gen1 operation SMBus switch initialization Delivers up to 48 GBps (384 Gbps) of switching capacity Common switch configurations are supported with pin strap- ping (no external components) Supports 128 Bytes to 2 KB maximum payload size Supports in-system Serial EEPROM initialization/program- Low latency cut-through architecture ming Supports one virtual channel and eight traffic classes Quality of Service (QoS) Standards and Compatibility Port arbitration PCI Express Base Specification 2.0 compliant Round robin Implements the following optional PCI Express features Request metering Advanced Error Reporting (AER) on all ports IDT proprietary feature that balances bandwidth among End-to-End CRC (ECRC) switch ports for maximum system throughput Access Control Services (ACS) High performance switch core architecture Power Budgeting Enhanced Capability Combined Input Output Queued (CIOQ) switch architecture Device Serial Number Enhanced Capability with large buffers Sub-System ID and Sub-System Vendor ID Capability Multicast Internal Error Reporting ECN Compliant to the PCI-SIG multicast ECN Multicast ECN Supports arbitrary multicasting of Posted transactions VGA and ISA enable Supports 64 multicast groups Multicast overlay mechanism support L0s and L1 ASPM ECRC regeneration support ARI ECN Clocking Port Configurability Supports 100 MHz and 125 MHz reference clock frequencies x4 and x8 ports Flexible port clocking modes Ability to merge adjacent x4 ports to create a x8 port Common clock Automatic per port link width negotiation Non-common clock (x8 x4 x2 x1) Local port clock with SSC and port reference clock input Crosslink support Hot-Plug and Hot Swap Automatic lane reversal Hot-plug controller on all ports Autonomous and software managed link width and speed Hot-plug supported on all downstream switch ports control 2 All ports support hot-plug using low-cost external I C I/O Per lane SerDes configuration expanders IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 59 December 12, 2013IDT 89HPES48H12AG2 Datasheet Direct package pin support for hot-plug on 5 ports Power Supplies Configurable presence detect supports card and cable appli- Requires only two power supply voltages (1.0 V and 2.5 V) cations Note that a 3.3V is preferred for V I/O DD GPE output pin for hot-plug event notification No power sequencing requirements Enables SCI/SMI generation for legacy operating system Packaged in a 35mm x 35mm 1156-ball Flip Chip BGA with support 1mm ball spacing Hot-swap capable I/O Product Description Power Management Utilizing standard PCI Express interconnect, the PES48H12AG2 Supports D0, D3hot and D3 power management states provides the most efficient fan-out solution for applications requiring Active State Power Management (ASPM) high throughput, low latency, and simple board layout with a minimum Supports L0, L0s, L1, L2/L3 Ready and L3 link states number of board layers. It provides 48 GBps (384 Gbps) of aggregated, Configurable L0s and L1 entry timers allow performance/ full-duplex switching capacity through 48 integrated serial lanes, using power-savings tuning proven and robust IDT technology. Each lane provides 5 GT/s of band- Supports PCI Express Power Budgeting Capability width in both directions and is fully compliant with PCI Express Base SerDes power savings Specification, Revision 2.0. Supports low swing / half-swing SerDes operation The PES48H12AG2 is based on a flexible and efficient layered SerDes optionally turned-off in D3hot architecture. The PCI Express layer consists of SerDes, Physical, Data SerDes associated with unused ports are turned-off Link and Transaction layers in compliance with PCI Express Base spec- SerDes associated with unused lanes are placed in a low ification Revision 2.0. The PES48H12AG2 can operate either as a store power state and forward or cut-through switch. It supports eight Traffic Classes 54 General Purpose I/O (TCs) and one Virtual Channel (VC) with sophisticated resource Reliability, Availability and Serviceability (RAS) management to enable efficient switching and I/O connectivity for ECRC support servers, storage, and embedded processors with limited connectivity. AER on all ports The PES48H12AG2 is a partitionable PCIe switch. This means that SECDED ECC protection on all internal RAMs in addition to operating as a standard PCI express switch, the End-to-end data path parity protection PES48H12AG2 ports may be partitioned into groups that logically Checksum Serial EEPROM content protected operate as completely independent PCIe switches. Figure 2 illustrates a three partition PES48H12AG2 configuration. Autonomous link reliability (preserves system operation in the presence of faulty links) Ability to generate an interrupt (INTx or MSI) on link up/down transitions Test and Debug On-chip link activity and status outputs available for several ports including the upstream ports Per port link activity and status outputs available using 2 external I C I/O expander for all remaining ports SerDes test modes Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG 2 of 59 December 12, 2013