89PES32T8 32-Lane 8-Port Data Sheet PCI Express Switch Flexible Architecture with Numerous Configuration Options Device Overview Automatic per port link width negotiation to x8, x4, x2 or x1 The 89HPES32T8 is a member of the IDT PRECISE family of PCI Automatic lane reversal on all ports Express switching solutions. The PES32T8 is a 32-lane, 8-port periph- Automatic polarity inversion on all lanes eral chip that performs PCI Express packet switching with a feature set Ability to load device configuration from serial EEPROM optimized for high performance applications such as servers, storage, Legacy Support and communications/networking. It provides connectivity and switching functions between a PCI Express upstream port and up to seven down- PCI compatible INTx emulation stream ports and supports switching between downstream ports. Bus locking Highly Integrated Solution Features Requires no external components High Performance PCI Express Switch Incorporates on-chip internal memory for packet buffering and queueing Thirty-two 2.5 Gbps PCI Express lanes Integrates thirty-two 2.5 Gbps embedded SerDes with 8B/10B Eight switch ports encoder/decoder (no separate transceivers needed) Upstream port configurable up to x8 Reliability, Availability, and Serviceability (RAS) Features Downstream ports configurable up to x8 Supports ECRC and Advanced Error Reporting Low-latency cut-through switch architecture Internal end-to-end parity protection on all TLPs ensures data Support for Max Payload Size up to 2048 bytes integrity even in systems that do not implement end-to-end One virtual channel CRC (ECRC) Eight traffic classes Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O PCI Express Base Specification Revision 1.1 compliant Compatible with Hot-Plug I/O expanders used on PC and server motherboards Block Diagram 8-Port Switch Core / 32 PCI Express Lanes Port Frame Buffer Route Table Scheduler Arbitration Transaction Layer Transaction Layer Transaction Layer Data Link Layer Data Link Layer Data Link Layer Multiplexer / Demultiplexer Multiplexer / Demultiplexer Multiplexer / Demultiplexer Phy Phy Phy Phy Phy Phy Phy Phy Phy Phy Phy Phy Logical Logical Logical Logical Logical Logical Logical Logical Logical Logical Logical Logical Layer Layer Layer Layer Layer Layer Layer Layer Layer Layer Layer Layer SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes (Port 1) (Port 0) (Port 7) Figure 1 Internal Block Diagram IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 37 March 25, 2008 2007 Integrated Device Technology, Inc.IDT 89PES32T8 Data Sheet Power Management The PES32T8 is based on a flexible and efficient layered architec- ture. The PCI Express layers consist of SerDes, Physical, Data Link and Utilizes advanced low-power design techniques to achieve low Transaction layers. The PES32T8 can operate either as a store and typical power consumption forward switch or a cut-through switch and is designed to switch Supports PCI Power Management Interface specification memory and I/O transactions. It supports eight Traffic Classes (TCs) (PCI-PM 1.1) and one Virtual Channel (VC) with sophisticated resource management Supports device power management states: D0, D3 and hot to enable efficient switching and I/O connectivity. D3 cold Unused SerDes are disabled Testability and Debug Features Ability to read and write any internal register via the SMBus Processor Processor Sixteen General Purpose Input/Output Pins Each pin may be individually configured as an input or output Each pin may be individually configured as an interrupt input Memory North Memory Memory Some pins have selectable alternate functions Memory Bridge Packaged in a 31mm x 31mm 500-ball BGA with 1mm ball x8 spacing PES32T8 Product Description Utilizing standard PCI Express interconnect, the PES32T8 provides x4 x8 x4 x8 the most efficient I/O connectivity solution for applications requiring high throughput, low latency, and simple board layout with a minimum I/O I/O I/O I/O number of board layers. It provides connectivity for up to 8 ports across PCI Express 10GbE 10GbE SATA SATA Slots 32 integrated serial lanes. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specifica- tion revision 1.1. Figure 2 I/O Expansion Application 2 of 37 March 25, 2008