Version 1.1 2007 . PEX 8112 Features General Features o Forward and Reverse bridging ExpressLane PCI Express to PCI Bridge o 144-ball BGA package with standard 1.0 mm pitch (13mm x 13mm) o 161-ball BGA package with fine Reversible Bridge in a Tiny Package 0.65 mm pitch (10mm x 10mm) o Low power 400 milliwatts The PLX Technology PEX 8112 bridge enables designers to migrate legacy PCI bus o EEPROM configuration option with interfaces to the new advanced serial PCI Express. This is ideal for including SPI existing PCI ICs on a PCI Express Adapter Board, such as the new ExpressCard o Internal 8Kbyte shared RAM or AdvancedMC standards. The 13mm x 13mm standard BGA package or 10mm o 1.5 V core supply voltage x 10mm fine BGA package offerings makes the PEX 8112 bridge well suited for o JTAG applications where board real estate is at a premium. With its low power 0.15 micron o Four (4) GPIO pins for maximum CMOS design, the PEX 8112 consumes only about 400 mW of power. design flexibility o Extensive PME support including Forward and Reverse Bridging D0 and D0 , D1, D2 and D3 Active Hot The PEX 8112 supports forward and reverse bridging as defined by the and D3 Cold PCI Express-to-PCI/PCI-X Bridge Specification 1.0. In forward mode, the bridge o Leaded and Lead-free standard pitch allows legacy PCI chips and adapters to be used with new PCI Express processor packaging available systems. Reverse bridge operation allows conventional PCI processors and chipsets o Lead-free fine pitch packaging only to configure and control advanced PCI Express switches and endpoints. The reverse o Industrial Temperature: -40 to +85C PEX 8112 not only allows complete configuration of a downstream PCI Express Integrated PCI Express Interface system from the PCI bus, but it also handles limited PCI Express root functions for o PCI Express Base 1.0a compliant reverse interrupt and Power Management Events. o x1 Link, dual-simplex, 2.5 Gbps per direction PCI Bus (32-bit, 33/66 MHz) o One virtual channel Block Diagram o Automatic LVDS polarity reversal The PEX 8112 is equipped with a o 128 byte maximum payload size standard PCI Express port that o Link CRC operates as a single, x1 link with a o Link power management maximum of 250 Megabytes per o Flow control buffering second of throughput per transmit o PCI Express transaction queues for PCI Master and Target Interface Logic and receive direction. The single 2.5 eight (8) outstanding TLPs Gbps integrated SerDes delivers the PCI Interface highest bandwidth with the lowest Configuration 8K Shared o PCI v.3.0: 32 bits, up to 66 MHz FIFOs possible pin count using LVDS Registers RAM o PCI Power Management 1.1 technology. o Internal arbiter supports up to 4 PCI Express Transaction Layer external masters REQ /GNT The PEX 8112 has a single parallel (Packet Construction Logic) signals bus segment supporting the PCI v.3.0 PCI Express Data Link Layer o 3.3V I/O and 5V tolerant PCI protocol, and a 32-bit wide parallel o Message Signal Interrupt (MSI) data path running up to 66MHz. PCI Express PHY Layer support The device supports internal queues o Provides PCI clock output with flow control features to optimize j o Four mailbox registers for messaging throughput and traffic flow. o VGA and ISA Enable registers for legacy operation PCI Express Link (1 lane, 2.5 GHz) Figure 1. PEX 8112 Block Diagram Embedded Host Platform Reverse Bridge Design Applications The PEX 8112 supports Reverse bridging, enabling designers to utilize the latest PCI Express silicon with widely entrenched ExpressCard Adapter Forward Bridge PCI host systems. Reverse bridging allows the host processor The PEX 8112 can be used to quickly upgrade legacy PCI to reside on the PCI bus the PEX 8112 will accept adapter board designs to be compatible with PCI Express configuration cycles from the PCI side and manage the PCI standard interface slots. In Figure 2, an existing CardBus IC Express interface as a secondary entity within the PCI is converted for use on an ExpressCard with the addition of software model as in Figure 3. the single-chip PEX 8112. PCI SloPCI Slottss ExpressCarExpressCardd PCI BusPCI Bus CardBusCardBus PEXPEX PCI BuPCI Buss PCIPCIPCI SiliconSilicon 81128111 HostHostHost CPUCPUCPU PCIPCI PEXPEX ExpressExpress 81128111 ASASIICC Figure 2. Forward Bridge in ExpressCard Figure 3. Reverse Bridge with PCI CPU Development Tools PEX 8112 Reference Design Kits (RDK) enable rapid customer design. The Reverse Bridge RDK (Figure 4) includes a standard PCI connector (card-edge) and a standard PCI Express slot on the secondary side. The Forward Bridge RDK (Figure 5) includes the PEX 8112 with a single x1 PCI Express port (card-edge) and four PCI slots on the secondary side. Each PEX 8112RDK can be installed in a motherboard to evaluate PEX 8112 features and validate customer software. EEPROM PEX HH JJ ee TT aa AA dd GG ee 8112 Bridge rr EEPROM JTAG Header PEX 8114 PEX EEPROM Bridge 8112 Figure 4. Reverse Bridge RDK Figure 5. Forward Bridge RDK Product Ordering Information Part Number Description PEX8112-AA66BI PCI Express to PCI Bridge, Standard-Pitch BGA Package, Leaded PLX Technology, Inc. PEX8112-AA66BI F PCI Express to PCI Bridge, Standard-Pitch BGA Package, Lead Free 870 Maude Ave. Sunny vale, CA 94085 USA PEX8112-AA66FBI F PCI Express to PCI Bridge, Fine-Pitch BGA Package, Lead-Free Tel: 1-. 408-774-9060 PEX8112RDK-F Forward Bridge Reference Design Kit Fax: 1-408-774-2169 Email: info plxtech.com PEX8112RDK-R Reverse Bridge Reference Design Kit Web Site: www.plxtech.com Please visit the PLX Web site at
