89HPES3T3 3-Lane 3-Port Data Sheet PCI Express Switch u Highly Integrated Solution Device Overview Requires no external components The 89HPES3T3 is a member of IDTs PRECISE family of PCI Incorporates on-chip internal memory for packet buffering and Express switching solutions. The PES3T3 is a 3-lane, 3-port peripheral queueing chip that performs PCI Express Base switching. It provides connectivity Integrates three 2.5 Gbps embedded SerDes with 8B/10B and switching functions between a PCI Express upstream port and up to encoder/decoder (no separate transceivers needed) four downstream ports and supports switching between downstream u Reliability, Availability, and Serviceability (RAS) Features ports. Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end Features CRC (ECRC) u High Performance PCI Express Switch Supports ECRC and Advanced Error Reporting Three 2.5Gbps PCI Express lanes Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O Three switch ports Compatible with Hot-Plug I/O expanders used on PC mother- x1 Upstream port boards u Two x1 Downstream ports Power Management Low latency cut-through switch architecture Utilizes advanced low-power design techniques to achieve low Support for Max payload sizes up to 256 bytes typical power consumption One virtual channel Supports PCI Power Management Interface specification (PCI- Eight traffic classes PM 1.2) PCI Express Base Specification Revision 1.1 compliant Unused SerDes are disabled. u Flexible Architecture with Numerous Configuration Options Supports Advanced Configuration and Power Interface Speci- fication, Revision 2.0 (ACPI) supporting active link state Automatic lane reversal on all ports u Testability and Debug Features Automatic polarity inversion on all lanes Ability to load device configuration from serial EEPROM Built in Pseudo-Random Bit Stream (PRBS) generator u Legacy Support Numerous SerDes test modes Ability to bypass link training and force any link into any mode PCI compatible INTx emulation Provides statistics and performance counters Bus locking Block Diagram 3-Port Switch Core / 3 PCI Express Lanes Port Frame Buffer Route Table Scheduler Arbitration Transaction Layer Transaction Layer Transaction Layer Data Link Layer Data Link Layer Data Link Layer Mux / Demux Mux / Demux Mux / Demux Phy Phy Phy Logical Logical Logical Layer Layer Layer SerDes SerDes SerDes (Port 2) (Port 0) (Port 3) Figure 1 Internal Block Diagram IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 31 June 12, 2014IDT 89HPES3T3 Data Sheet u Five General Purpose Input/Output Pins Each pin may be individually configured as an input or output Each pin may be individually configured as an interrupt input Four pins have selectable alternate functions u Option A Package: 13mm x 13mm 144-ball BGA with 1mm ball spacing u Option B Package: 10mm x 10mm 132-ball QFN with 1mm ball spacing Product Description Utilizing standard PCI Express interconnect, the PES3T3 provides the most efficient fan-out solution for applications requiring x1 connectivity, low latency, and simple board layout with a minimum number of board layers. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification 1.1. The PES3T3 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transac- tion layers in compliance with PCI Express Base specification Revision 1.1. The PES3T3 can operate either as a store and forward or cut-through switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management to allow efficient switching for applications requiring additional narrow port connectivity and also some high-end connectivity. Processor Processor Memory North Memory Memory Memory Bridge South Bridge x1 PES3T3 x1 x1 GE 1394 LOM Figure 2 I/O Expansion Application SMBus Interface The PES3T3 contains an SMBus master interface. This master interface allows the default configuration register values of the PES3T3 to be over- ridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O expander. Two pins make up the SMBus master interface. These pins consist of an SMBus clock pin and an SMBus data pin. Hot-Plug Interface The PES3T3 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES3T3 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, when- ever the state of a Hot-Plug output needs to be modified, the PES3T3 generates an SMBus transaction to the I/O expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate function of GPIO) of the PES3T3. In response to an I/O expander interrupt, the PES3T3 generates an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander. 2 of 31 June 12, 2014