89HPES4T4G2 4-Lane 4-Port Data Sheet Gen2 PCI Express Switch Legacy Support Device Overview The 89HPES4T4G2, a 4-lane 4-port Gen2 PCI Express switch, is a PCI compatible INTx emulation member of IDTs PRECISE family of PCI Express switching solutions. Bus locking The PES4T4G2 is a peripheral chip that performs PCI Express base Highly Integrated Solution switching with a feature set optimized for servers, storage, communica- Requires no external components tions, and consumer applications. It provides connectivity and switching Incorporates on-chip internal memory for packet buffering and functions between a PCI Express upstream port and three downstream queueing ports or peer-to-peer switching between downstream ports. Integrates four 5 Gbps embedded SerDes with 8b/10b encoder/decoder (no separate transceivers needed) Features Receive equalization (RxEQ) High Performance PCI Express Switch Reliability, Availability, and Serviceability (RAS) Features Four Gen2 PCI Express lanes supporting 5 Gbps and Internal end-to-end parity protection on all TLPs ensures data 2.5 Gbps operations integrity even in systems that do not implement end-to-end Four switch ports CRC (ECRC) One x1 upstream port Supports ECRC and Advanced Error Reporting Three x1 downstream ports All internal data and control RAMs are SECDED ECC Low latency cut-through switch architecture protected Support for Max Payload Size up to 2Kbytes Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O Supports one virtual channel and eight traffic classes Compatible with Hot-Plug I/O expanders used on PC mother- PCI Express Base Specification Revision 2.0 compliant boards Flexible Architecture with Numerous Configuration Options Supports Hot-Swap Automatic lane reversal on all ports Automatic polarity inversion Ability to load device configuration from serial EEPROM Block Diagram 4-Port Switch Core / 4 Gen2 PCI Express Lanes Port Frame Buffer Route Table Scheduler Arbitration Transaction Layer Transaction Layer Transaction Layer Transaction Layer Data Link Layer Data Link Layer Data Link Layer Data Link Layer Mux / Demux Mux / Demux Mux / Demux Mux / Demux Phy Phy Phy Phy Logical Logical Logical Logical Layer Layer Layer Layer SerDes SerDes SerDes SerDes (Port 1) (Port 3) (Port 0) (Port 2) Figure 1 Internal Block Diagram IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 30 May 23, 2013 DSC 6928IDT 89HPES4T4G2 Data Sheet Power Management Utilizes advanced low-power design techniques to achieve low typical power consumption Processor Processor Support PCI Power Management Interface specification (PCI- PM 2.0) Supports device power management states: D0, D3 and hot Memory North Memory D3 Memory Memory cold Bridge Support for PCI Express Active State Power Management (ASPM) link state x1 Supports link power management states: L0, L0s, L1, L2/L3 Ready and L3 PES4T4G2 Supports PCI Express Power Budgeting Capability Configurable SerDes power consumption x1 x1 x1 Supports optional PCI-Express SerDes Transmit Low-Swing Voltage Mode I/O I/O I/O I/O PCI Express Supports numerous SerDes Transmit Voltage Margin 4xGbE 4xGbE SATA SATA Slot settings Unused SerDes are disabled Figure 2 I/O Expansion Application Testability and Debug Features Built in Pseudo-Random Bit Stream (PRBS) generator SMBus Interface Numerous SerDes test modes The PES4T4G2 contains two SMBus interfaces. The slave interface Ability to read and write any internal register via the SMBus provides full access to the configuration registers in the PES4T4G2, Ability to bypass link training and force any link into any mode allowing every configuration register in the device to be read or written Provides statistics and performance counters by an external agent. The master interface allows the default configura- General Purpose Input/Output Pins tion register values of the PES4T4G2 to be overridden following a reset with values programmed in an external serial EEPROM. The master Each pin may be individually configured as an input or output interface is also used by an external Hot-Plug I/O expander. Each pin may be individually configured as an interrupt input Some pins have selectable alternate functions Two pins make up each of the two SMBus interfaces. These pins Packaged in a 19mm x 19mm, 324-ball BGA with 1mm ball consist of an SMBus clock pin and an SMBus data pin. The Master spacing SMBus address is hardwired to 0x50, and the slave SMBus address is hardwired to 0x77. Product Description As shown in Figure 3, the master and slave SMBuses may be used Utilizing standard PCI Express interconnect the PES4T4G2 provides in a unified or split configuration. In the unified configuration, shown in the most efficient high-performance I/O connectivity device for applica- Figure 3(a), the master and slave SMBuses are tied together and the tions requiring high throughput, low latency and simple board layout. It PES4T4G2 acts both as a SMBus master as well as a SMBus slave on provides PCI Express connectivity across 4 lanes and 4 ports. Each this bus. This requires that the SMBus master or processor that has lane provides 5 Gbps of bandwidth in both directions and is fully access to PES4T4G2 registers supports SMBus arbitration. In some compliant with PCI Express Base specification 2.0. systems, this SMBus master interface may be implemented using general purpose I/O pins on a processor or micro controller, and may The PES4T4G2 is based on a flexible and efficient layered architec- not support SMBus arbitration. To support these systems, the ture. The PCI Express layer consists of SerDes, Physical, Data Link and PES4T4G2 may be configured to operate in a split configuration as Transaction layers in compliance with PCI Express Base specification shown in Figure 3(b). Revision 2.0. The PES4T4G2 can operate either as a store and forward or cut-through switch and is designed to switch memory and I/O transac- In the split configuration, the master and slave SMBuses operate as tions. It supports eight Traffic Classes (TCs) and one Virtual Channel two independent buses and thus multi-master arbitration is never (VC) with sophisticated resource management to enable efficient required. The PES4T4G2 supports reading and writing of the serial switching and I/O connectivity for servers, storage, and embedded EEPROM on the master SMBus via the slave SMBus, allowing in processors with limited connectivity. system programming of the serial EEPROM. 2 of 30 May 23, 2013