PEX8603, PCI Express Gen 2 Switch, 3 Lanes, 3 Ports
The ExpressLane PEX8603 device offers PCI Express switching capability
Highlights
enabling users to add scalable high bandwidth non-blocking interconnection
PEX8603 General Features
to a wide variety of applications including control plane applications,
o 3-lane, 3-port PCIe Gen2 switch
consumer applications and embedded systems. The PEX8603 is well suited
Integrate 5.0 GT/s SerDes
2
for fan-out and peer-to-peer applications.
o 10 x 10mm , 136-pin QFN
package
o Typical Power: 0.7 Watts
Low Packet Latency & High Performance
The PEX8603 architecture supports packet cut-thru with a maximum latency of
PEX8603 Key Features
o Standards Compliant 250ns in x1 to x1 configuration. This, combined with low power consumption
PCI Express Base Specification, r2.1
and non-blocking internal switch architecture, provides full line rate on all ports
(backwards compatible w/ PCIe
for low-power applications such as consumer and embedded. The low latency
1.0a/1.1)
PCI Power Management Spec, r1.2
enables applications to achieve high throughput and performance. In addition to
Microsoft Windows 7 Compliant
low latency, the device supports a max payload size of 256 bytes.
Dynamic SerDes speed control
o High Performance
Data Integrity
Non-blocking switch fabric
Full line rate on all ports The PEX8603 provides end-to-end CRC protection (ECRC) and Poison bit
Packet Cut-Thru with 250ns max
support to enable designs that require guaranteed error-free packets. PLX also
packet latency (x1 to x1)
supports data path parity and memory (RAM) error correction as packets pass
256B Max Payload Size
through the switch.
o Flexible Configuration
Ports configurable as x1, x2
Registers configurable with strapping
Power Management and Reference Clock Buffers
2
pins, EEPROM, I C, or host software
Reference Clock Buffered Output The PEX8603 supports the following power management states: L0, L0s, L1,
signals for downstream ports
L2/L3 Ready, L2 and L3. Moreover, the PEX8603 supports Vaux along with the
Lane and polarity reversal
external signal WAKE# and the in-band Beacon for the PCIe endpoints to use to
Compatible with PCIe 1.0a PM
inform the system host to exit the low power savings mode.
o Quality of Service (QoS)
The PEX 8603 supports two pairs of buffered, 100 MHz HCSL output clocks,
Eight traffic classes per port
Round-robin source port arbitration
one pair for each downstream port of the switch. Each clock output pair can be
Relaxed PCI Ordering
disabled by software or serial EEPROM when not in use, for additional power
savings. This feature greatly reduces system BOM cost by eliminating the need
o Reliability, Availability,
for extra clock buffers on the PCB.
Serviceability
visionPAK
Per Port Performance Monitoring
Per port payload & header counters
Interoperability
SerDes Eye Capture
The PEX8603 is designed to be fully compliant with the PCI Express Base
Error Injection and Loopback
2
All ports hot plug capable thru I C
Specification r2.1 and is backwards compatible to PCI Express Base
(Hot-Plug Controller on every port)
Specification r1.1 and r1.0a. Additionally each port supports auto-negotiation and
Data Path parity
polarity reversal. Furthermore, the PEX8603 is designed for Microsoft Windows
Memory (RAM) Error Correction
signals
7 compliance. All PLX switches undergo thorough interoperability testing in
INTA# and FATAL_ERR#
PLXs Interoperability Lab and compliance testing at the PCI-SIG plug-fest to
Advanced Error Reporting
Port Status bits and GPIO available ensure compatibility with PCI Express devices in the market.
Per port error diagnostics
JTAG AC/DC boundary scan
Device Operation Configuration Flexibility
o Power Management
The PEX8603 provides several ways to configure its operations. The device can
WAKE#, Beacon, Vaux support
be configured through strapping pins, I2C interface, CPU configuration cycles
and/or an optional serial EEPROM. This allows for easy debug during the
development phase and functional monitoring during the operation phase.
PLX Technology, www.plxtech.com Page 1 of 3 8/17/2011, Version 1.1 PEX8603, PCI Express Gen 2 Switch, 3 Lanes, 3 Ports
With WAKE#/Beacon support integrated in the switch, the
Flexible Port Configurations
PEX8603 is well suited for low power consumer applications
The PEX8603 flexible architecture supports a number of port
such as that described in Figure 2 of a dual-band wireless
configurations as required by the target applications as shown in
adapter.
figure 1 below.
Modem Set-top Box
x2 x1
With its small footprint, the PEX8603 is ideal for consumer
applications. Figure 3 shows a high level diagram for a modem
set-top box. The PEX8603 provides connectivity to a WiFi
PEX 8603 PEX 8603
controller for immediate use as well as future expansion.
x1 x1 x1
Figure 1. Port Configurations
SerDes Power and Signal Management
The PEX8603 provides low power capability that is fully
compliant with the PCI Express power management
specification. In addition, the SerDes physical links can be
turned off when unused for even lower power. The PEX8603
supports software control of the SerDes outputs to allow
optimization of power and signal strength in a system. The PLX
SerDes implementation supports four levels of power off, low,
Figure 3. Modem Set-top Box Block Diagram
typical, and high. The SerDes block also supports loop-back
modes and advanced reporting of error conditions, which
enables efficient debug and management of the entire system.
Fan-Out
The PEX8603 can be used in as a fan-out switch to provide
Port Arbitration and QoS
additional x1ports. The PEX8603 SerDes can function at
The PEX8603 switch supports hardware fixed Round-Robin
2.5GT/s or 5
Ingress Port Arbitration. The PEX8603 also supports Eight
Traffic Classes (TCs) as defined in the PCIe specification.
CPU
Applications
Suitable for fan-out, consumer, control plane applications,
PCH
and embedded systems, PEX8603 is suited for a wide variety x1 .. x1
Gen1
of form factors and applications.
PEX 8603
Dual-Band Wireless Adapter
x1
The PEX8603 switch, with its small package and low power can
2.5GT/s; 5.0GT/s
be used in consumer applications such as a dual-band wireless
adapter.
Figure 4. Fan-out
Bandwidth Bridge
There are three PCIe lanes available in the PEX8603. Each one
can represent an individual port or alternatively two can be
joined to form a x2 port. A x2 port can provide double the
bandwidth of a x1 port when all lanes are operating at the same
data rates (all at 2.5GT/s or 5.0GT/s). In some instances, the
need to match the bandwidth between devices running at
Figure 2. Dual-band Wireless Adapter
different data rates (2.5GT/s vs 5.0GT/s) is required to sustain
the performance of the faster device. Figure 5 provides an
PLX Technology, www.plxtech.com Page 2 of 3 8/17/2011, Version 1.1