PCA9541BS/03,118 NXP

PCA9541 2 2-to-1 I C-bus master selector with interrupt logic and reset Rev. 7.1 24 June 2015 Product data sheet 1. General description 2 The PCA9541 is a 2-to-1 I C-bus master selector designed for high reliability dual master 2 I C-bus applications where system operation is required, even when one master fails or the controller card is removed for maintenance. The two masters (for example, primary 2 and back-up) are located on separate I C-buses that connect to the same downstream 2 2 2 I C-bus slave devices. I C-bus commands are sent by either I C-bus master and are used to select one master at a time. Either master at any time can gain control of the slave devices if the other master is disabled or removed from the system. The failed master is isolated from the system and will not affect communication between the on-line master 2 and the slave devices on the downstream I C-bus. Two versions are offered for different architectures. PCA9541/01 with channel 0 selected at start-up and PCA9541/03 with no channel selected after start-up. The interrupt outputs are used to provide an indication of which master has control of the bus. One interrupt input (INT IN) collects downstream information and propagates it to 2 the 2 upstream I C-buses (INT0 and INT1) if enabled. INT0 and INT1 are also used to let the previous bus master know that it is not in control of the bus anymore and to indicate the completion of the bus recovery/initialization sequence. Those interrupts can be disabled and will not generate an interrupt if the masking option is set. A bus recovery/initialization if enabled sends nine clock pulses, a not acknowledge, and a 2 STOP condition in order to set the downstream I C-bus devices to an initialized state before actually switching the channel to the selected master. An interrupt is sent to the upstream channel when the recovery/initialization procedure is completed. 2 An internal bus sensor senses the downstream I C-bus traffic and generates an interrupt if a channel switch occurs during a non-idle bus condition. This function is enabled when the PCA9541 recovery/initialization is not used. The interrupt signal informs the master 2 that an external I C-bus recovery/initialization needs to be performed. It can be disabled and an interrupt will not be generated. The pass gates of the switches are constructed such that the V pin can be used to limit DD the maximum high voltage, which will be passed by the PCA9541. This allows the use of different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V devices can communicate with 5 V devices without any additional protection. The PCA9541 does not isolate the capacitive loading on either side of the device, so the designer must take into account all trace and device capacitances on both sides of the device, and pull-up resistors must be used on all channels. External pull-up resistors pull the bus to the desired voltage level for each channel. All I/O pins are 6.0 V tolerant.PCA9541 NXP Semiconductors 2 2-to-1 I C-bus master selector with interrupt logic and reset An active LOW reset input allows the PCA9541 to be initialized. Pulling the RESET pin 2 LOW resets the I C-bus state machine and configures the device to its default state as does the internal Power-On Reset (POR) function. 2. Features and benefits 2-to-1 bidirectional master selector 2 I C-bus interface logic compatible with SMBus standards PCA9541/01 powers up with Channel 0 selected PCA9541/03 powers up with no channel selected and either master can take control of the bus Active LOW interrupt input 2 active LOW interrupt outputs Active LOW reset input 2 4 address pins allowing up to 16 devices on the I C-bus 2 Channel selection via I C-bus Bus initialization/recovery function Bus traffic sensor Low R switches on Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses No glitch on power-up Supports hot insertion Software identical for both masters Low standby current Operating power supply voltage range of 2.3 V to 5.5 V 6.0 V tolerant inputs 0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO16, TSSOP16, HVQFN16 3. Applications High reliability systems with dual masters Gatekeeper multiplexer on long single bus Bus initialization/recovery for slave devices without hardware reset Allows masters without arbitration logic to share resources PCA9541 7 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 7.1 24 June 2015 2 of 42