PCA9555 2 16-bit I C-bus and SMBus I/O port with interrupt Rev. 08 22 October 2009 Product data sheet 1. General description The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallel 2 Input/Output (GPIO) expansion for I C-bus/SMBus applications and was developed to 2 enhance the NXP Semiconductors family of I C-bus I/O expanders. The improvements include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O conguration, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc. The PCA9555 consists of two 8-bit Conguration (Input or Output selection) Input, Output and Polarity Inversion (active HIGH or active LOW operation) registers. The system master can enable the I/Os as either inputs or outputs by writing to the I/O conguration bits. The data for each Input or Output is kept in the corresponding Input or Output register. The polarity of the read register can be inverted with the Polarity Inversion 2 register. All registers can be read by the system master. Although pin-to-pin and I C-bus address compatible with the PCF8575, software changes are required due to the enhancements, and are discussed in Application Note AN469. The PCA9555 open-drain interrupt output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. 2 Three hardware pins (A0, A1, A2) vary the xed I C-bus address and allow up to eight 2 2 devices to share the same I C-bus/SMBus. The xed I C-bus address of the PCA9555 is the same as the PCA9554, allowing up to eight of these devices in any combination to 2 share the same I C-bus/SMBus. 2. Features n Operating power supply voltage range of 2.3 V to 5.5 V n 5 V tolerant I/Os n Polarity Inversion register n Active LOW interrupt output n Low standby current n Noise lter on SCL/SDA inputs n No glitch on power-up n Internal power-on reset n 16 I/O pins which default to 16 inputs n 0 Hz to 400 kHz clock frequency n ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101PCA9555 NXP Semiconductors 2 16-bit I C-bus and SMBus I/O port with interrupt n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA n Six packages offered: DIP24, SO24, SSOP24, TSSOP24, HVQFN24 and HWQFN24 3. Ordering information Table 1. Ordering information Type number Package Name Description Version PCA9555N DIP24 plastic dual in-line package 24 leads (600 mil) SOT101-1 PCA9555D SO24 plastic small outline package 24 leads SOT137-1 body width 7.5 mm PCA9555DB SSOP24 plastic shrink small outline package 24 leads SOT340-1 body width 5.3 mm PCA9555PW TSSOP24 plastic thin shrink small outline package 24 leads SOT355-1 body width 4.4 mm PCA9555BS HVQFN24 plastic thermal enhanced very thin quad at package SOT616-1 no leads 24 terminals body 4 4 0.85 mm PCA9555HF HWQFN24 plastic thermal enhanced very very thin quad at SOT994-1 package no leads 24 terminals body 4 4 0.75 mm 3.1 Ordering options Table 2. Ordering options Type number Topside mark Temperature range PCA9555N PCA9555 - 40 C to +85 C PCA9555D PCA9555D - 40 C to +85 C PCA9555DB PCA9555 - 40 C to +85 C PCA9555PW PCA9555 - 40 C to +85 C PCA9555BS 9555 - 40 C to +85 C PCA9555HF P55H - 40 C to +85 C PCA9555 8 NXP B.V. 2009. All rights reserved. Product data sheet Rev. 08 22 October 2009 2 of 34