PCA9641 2 2-channel I C-bus master arbiter Rev. 2.1 27 October 2015 Product data sheet 1. General description 2 The PCA9641 is a 2-to-1 I C master demultiplexer with an arbiter function. It is designed 2 for high reliability dual master I C-bus applications where correct system operation is 2 required, even when two I C-bus masters issue their commands at the same time. The arbiter will select a winner and let it work uninterrupted, and the losing master will take 2 control of the I C-bus after the winner has finished. The arbiter also allows for queued requests where a master requests the downstream bus while the other master has control. 2 A race condition occurs when two masters try to access the downstream I C-bus at almost the same time. The PCA9641 intelligently selects one winning master and the losing master gains control of the bus after the winning master gives up the bus or the reserve time has expired. Multiple transactions can be done without interruption. The time needed for multiple transactions on the downstream bus can be reserved by programming the Reserve Time register. During the reserve time, the downstream bus cannot be lost. 2 Software reset allows a master to send a reset through the I C-bus to put the PCA9641s registers into the power-on reset condition. The Device ID of the PCA9641 can be read by the master and includes manufacturer, device type and revision. 2 When there is no activity on the downstream I C-bus over 100 ms, optionally the PCA9641 will disconnect the downstream bus to both masters to avoid a lock-up on the 2 I C-bus. The interrupt outputs are used to provide an indication of which master has control of the bus, and which master has lost the downstream bus. One interrupt input (INT IN) collects 2 downstream information and propagates it to the two upstream I C-buses (INT0 and INT1) if enabled. INT0 and INT1 are also used to let the master know if the shared mail box has any new mail or if the outgoing mail has not been read by the other master. Those interrupts can be disabled and will not generate an interrupt if the masking option is set. The pass gates of the switches are constructed such that the V pin can be used to limit DD the maximum high voltage, which will be passed by the PCA9641. This allows the use of different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V devices can communicate with 3.3 V devices without any additional protection. The PCA9641 does not isolate the capacitive loading on either side of the device, so the designer must take into account all trace and device capacitances on both sides of the device, and pull-up resistors must be used on all channels.PCA9641 NXP Semiconductors 2 2-channel I C-bus master arbiter External pull-up resistors pull the bus to the desired voltage level for each channel. All I/O pins are 3.6 V tolerant. An active LOW reset input allows the PCA9641A to be initialized. Pulling the RESET pin 2 LOW resets the I C-bus state machine and configures the device to its default state as does the internal Power-On Reset (POR) function. 2. Features and benefits 2-to-1 bidirectional master selector 2 Channel selection via I C-bus 2 I C-bus interface logic compatible with SMBus standards 2 active LOW interrupt outputs to master controllers Active LOW reset input Software reset Four address pins allowing up to 112 different addresses 2 Arbitration active when two masters try to take the downstream I C-bus at the same time The winning master controls the downstream bus until it is done, as long as it is within the reserve time 2 Bus time-out after 100 ms on an inactive downstream I C-bus (optional) Readable device ID (manufacturer, device type, and revision) Bus initialization/recovery function Low R switches on Allows voltage level translation between 1.8 V, 2.3 V, 2.5 V, 3.3 V and 3.6 V buses No glitch on power-up Supports hot insertion Software identical for both masters Operating power supply voltage range of 2.3 V to 3.6 V All I/O pins are 3.6 V tolerant Up to 1 MHz clock frequency ESD protection exceeds 6000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: TSSOP16, HVQFN16 3. Applications High reliability systems with dual masters Gatekeeper multiplexer on long single bus Bus initialization/recovery for slave devices without hardware reset Allows masters without arbitration logic to share resources PCA9641 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 2.1 27 October 2015 2 of 55