PCAL6534 2 Ultra low-voltage translating 34-bit Fm+ I C-bus/SMBus I/O expander with Agile I/O features, interrupt output and reset Rev. 1 11 January 2019 Product data sheet 1. General description The PCAL6534 is a 34-bit general purpose I/O expander that provides remote I/O 2 expansion for most microcontroller families via the Fast-mode Plus (Fm+) I C-bus interface. The ultra low-voltage interface allows for direct connection to a microcontroller operating down to 0.8 V. NXP I/O expanders provide a simple solution when additional I/Os are needed while keeping interconnections to a minimum, for example, in battery-powered mobile applications for interfacing to sensors, push buttons, keypad, etc. In addition to providing a flexible set of GPIOs, it simplifies interconnection of a processor running at one voltage level down to 0.8 V to I/O devices operating at a different voltage level 1.65 V to 5.5 V. The PCAL6534 has built-in level shifting feature that makes these devices extremely flexible in mixed power supply systems where communication between incompatible I/O voltages is required, allowing seamless communications with next-generation low voltage microprocessors and microcontrollers on the interface side (SDA/SCL) and peripherals at a higher voltage on the port side. There are two supply voltages for PCAL6534: V and V . V provides DD(I2C-bus) DD(P) DD(I2C-bus) the supply voltage for the interface at the master side (for example, a microcontroller) and the V provides the supply for core circuits and Port P. The bidirectional voltage level DD(P) translation in the PCAL6534 is provided through V . V should be DD(I2C-bus) DD(I2C-bus) connected to the V of the external SCL/SDA lines. This indicates the V level of the DD DD 2 I C-bus to the PCAL6534, while the voltage level on Port P of the PCAL6534 is determined by the V . DD(P) 2 The PCAL6534 fully meets the Fm+ I C-bus specification at speeds to 1 MHz and implements Agile I/O, which are additional features specifically designed to enhance the I/O. These additional features are: programmable output drive strength, latchable inputs, programmable pull-up/pull-down resistors, maskable interrupt, interrupt status register, programmable open-drain or push-pull outputs. 2 Additional Agile I/O Plus features include I C software reset and Device ID. Interrupts can be specified by level or edge, and can be cleared individually without disturbing the other interrupt events. Also, switch debounce hardware is implemented. At power-on, the I/Os are configured as inputs. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register, saving external logic gates. Programmable pull-up and pull-down resistors eliminate the need for discrete components.PCAL6534 NXP Semiconductors 2 Ultra low-voltage translating 34-bit Fm+ I C-bus/SMBus I/O expander The power-on reset puts the registers in their default state and initializes the 2 I C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to occur without depowering the part. The system master can also accomplish a reset via an 2 I C command and initialize all registers to their default state. The PCAL6534 open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state. As well, the INT output can be specified to activate on input pin edges. There are a large number of interrupt mask functions available to maximize flexibility. INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data 2 on its ports without communication via the I C-bus. Thus, the PCAL6534 can remain a simple slave device. The input latch feature holds or latches the input pin state and keeps the logic values that created the interrupt until the master can service the interrupt. This minimizes the hosts interrupt service response for fast moving inputs. The device Port P outputs have 25 mA sink capabilities for directly driving LEDs while consuming low device current. 2 One hardware pin (ADDR) can be used to program and vary the fixed I C-bus address 2 and allow up to four devices to share the same I C-bus or SMBus. 2. Features and benefits 2 I C-bus to parallel port expander 2 1 MHz Fast-mode Plus I C-bus 2 Operating power supply voltage range of 0.8 V to 3.6 V on the I C-bus side Allows bidirectional voltage-level translation and GPIO expansion between 0.8 V to 3.6 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V, 5.5 V Port P Low standby current consumption: 2.0 A typical at 3.3 V V DD(P) Schmitt trigger action allows slow input transition and better switching noise immunity at the SCL and SDA inputs V = 0.05 V (typical) at 0.8 V hys V = 0.18 V (typical) at 1.8 V hys V = 0.33 V (typical) at 3.3 V hys 2 5.5 V tolerant I/O ports and 3.6 V tolerant I C-bus pins Active LOW reset input (RESET) Open-drain active LOW interrupt output (INT) Internal power-on reset Noise filter on SCL/SDA inputs Latched outputs with 25 mA drive maximum capability for directly driving LEDs Latch-up performance exceeds 100 mA per JESD 78, Class II ESD protection exceeds JESD 22 2000 V Human-Body Model (A114-A) 1000 V Charged-Device Model (C101) Packages offered: VFBGA42 PCAL6534 All information provided in this document is subject to legal disclaimers. NXP B.V. 2019. All rights reserved. Product data sheet Rev. 1 11 January 2019 2 of 75