PCU9656B,118 NXP

PCU9656 2 24-bit UFm 5 MHz I C-bus 100 mA 40 V LED driver Rev. 1 8 December 2011 Product data sheet 1. General description 2 The PCU9656 is a UFm I C-bus controlled 24-bit LED driver optimized for voltage switch dimming and blinking 100 mA Red/Green/Blue/Amber (RGBA) LEDs. Each LEDn output has its own 8-bit resolution (256 steps) fixed frequency individual PWM controller that operates at 97 kHz (typical) with a duty cycle that is adjustable from 0 % to 99.6 % to allow the LED to be set to a specific brightness value. An additional 8-bit resolution (256 steps) group PWM controller has both a frequency of 190 Hz and an adjustable frequency between 24 Hz to once every 10.73 seconds with a duty cycle that is adjustable from 0 % to 99.6 % that is used to either dim or blink all LEDs with the same value. Each LEDn output can be off, on (no PWM control), set at its individual PWM controller value or at both individual and group PWM controller values. The PCU9656 operates with a supply voltage range of 2.3 V to 5.5 V and the 100 mA open-drain outputs allow voltages up to 40 V for the LED supply. The PCU9656 is one of the first LED controller devices in a new Ultra Fast-mode (UFm) family. UFm devices offer higher frequency (up to 5 MHz). The active LOW Output Enable input pin (OE) blinks all the LEDn outputs and can be used to externally PWM the outputs, which is useful when multiple devices need to be dimmed or blinked together without using software control. 2 Software programmable LED Group and three Sub Call I C-bus addresses allow all or 2 defined groups of PCU9656 devices to respond to a common I C-bus address, allowing for example, all red LEDs to be turned on or off at the same time or marquee chasing 2 effect, thus minimizing I C-bus commands. Six hardware address pins allow up to 64 devices on the same bus. The Software Reset (SWRST) Call allows the master to perform a reset of the PCU9656 2 through the I C-bus, identical to the Power-On Reset (POR) that initializes the registers to their default state causing the output NAND FETs to be OFF (LED off). This allows an easy and quick way to reconfigure all device registers to the same condition. A new feature to control LEDn output pattern is incorporated in the PCU9656. A new control byte called Chase Byte allows enabling or disabling of selective LEDn outputs depending on the value of the Chase Byte. This feature greatly reduces the number of bytes to be sent to the PCU9656 when repetitive patterns need to be displayed as in creating a marquee chasing effect.PCU9656 NXP Semiconductors 2 24-bit UFm 5 MHz I C-bus 100 mA 40 V LED driver 2. Features and benefits 24 LED drivers. Each output programmable at: Off On Programmable LED brightness Programmable group dimming/blinking mixed with individual LED brightness 2 5 MHz Ultra Fast-mode unidirectional I C-bus interface 256-step (8-bit) linear programmable brightness per LEDn output varying from fully off (default) to maximum brightness using a 97 kHz PWM signal 256-step group brightness control allows general dimming (using a 190 Hz PWM signal) from fully off to maximum brightness (default) 256-step group blinking with frequency programmable from 24 Hz to 10.73 s and duty cycle from 0 % to 99.6 % 24 open-drain outputs can sink between 0 mA to 100 mA and are tolerant to a maximum off state voltage of 40 V. No input function. Output state change programmable on the Acknowledge (bit 9, this bit is always set to 1 by master) or the STOP Command to update outputs byte-by-byte or all at the same time (default to Change on STOP). Active LOW Output Enable (OE) input pin allows for hardware blinking and dimming of the LEDs Six hardware address pins allow 64 PCU9656 devices to be connected to the same 2 UFm I C-bus and to be individually programmed 2 Four software programmable UFm I C-bus addresses (one LED Group Call address and three LED Sub Call addresses) allow groups of devices to be addressed at the same time in any combination (for example, one register used for All Call so that all 2 the PCU9656s on the I C-bus can be addressed at the same time and the second 1 register used for three different addresses so that of all devices on the bus can be 3 2 addressed at the same time in a group). Software enable and disable for I C-bus address. A Chase Byte allows execution of predefined ON/OFF pattern for the 24 LEDn outputs Software Reset feature (SWRST Call) allows the device to be reset through the 2 UFm I C-bus 25 MHz internal oscillator requires no external components Internal power-on reset Noise filter on USDA/USCL inputs Glitch-free LEDn outputs on power-up Supports hot insertion Low standby current Operating power supply voltage (V ) range of 2.3 V to 5.5 V DD 5.5 V tolerant inputs on non-LED pins 40 C to +85 C operation ESD protection exceeds 2000 V HBM per JESD22-A114, and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Package offered: LQFP48 PCU9656 All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 8 December 2011 2 of 45