PR601 Integrated Reader Module Rev. 3.0 12 November 2012 Product data sheet 219330 COMPANY PUBLIC 1. Introduction Delivering unprecedented integration, these module combines the functionality of multiple discrete ICs in a single package and enables the development of compact, cost-effective contactless reader systems for access and industrial applications. The module includes microcontroller functionality and support of multiple contactless reader protocols based on 13.56 MHz. The package contains two dies: 1. LPC1227FBD48/301 2. CLRC66301HN1 Not all pins of the LPC1227 specified in the data sheet are available at the reader module. Please refer to Section 9 Pinning information. The device does not implement any interconnection inside the package. This enables easy access to all signals during system development. 2. General description 2.1 CLRC663 The CLRC663 is a highly integrated transceiver IC for contactless communication at 13.56 MHz. This transceiver IC utilizes an outstanding modulation and demodulation concept completely integrated for different kinds of contactless communication methods and protocols at 13.56 MHz. The CLRC663 transceiver ICs support following different operating modes: Reader/Writer mode supporting ISO/IEC 14443A/MIFARE Reader/Writer mode supporting ISO/IEC 14443B Reader/Writer mode supporting FeliCa scheme Reader/Writer mode supporting ISO/IEC 15693 Reader/Writer mode supporting ICODE EPC UID/ EPC OTP Reader/Writer mode supporting ISO/IEC 18000-3 Mode 3 NFC P2P passive initiator The CLRC663 internal transmitter is able to drive a reader/writer antenna designed to communicate with ISO/IEC 14443A/MIFARE cards and transponders without additional active circuitry. The receiver module provides a robust and efficient implementation for PR601 NXP Semiconductors Integrated Reader Module demodulation and decoding signals from ISO 14443A/MIFARE compatible cards and transponders. The digital module manages the complete ISO 14443A framing and error detection (parity and CRC) functionality. The CLRC663 supports MIFARE 1K, MIFARE 4K, MIFARE Ultralight, MIFARE, Ultralight C, MIFARE PLUS and MIFARE DESFire products. The CLRC663 supports contactless communication and uses MIFARE higher transfer speeds up to 848 kBd in both directions. The CLRC663 supports all layers of the ISO/IEC 14443B reader/writer communication scheme, given correct implementation of additional components, like oscillator, power supply, coil etc. and provided that standardized protocols, for example, like ISO/IEC 14443-4 and/or ISO/IEC 14443B anticollision are correctly implemented. The use of this NXP IC according to ISO/IEC 14443B might infringe third party patent rights. A purchaser of this NXP IC has to take care for appropriate third party patent licenses. Enabled in Reader/Writer mode for FeliCa, the CLRC663 transceiver IC supports the FeliCa communication scheme. The receiver part provides a robust and efficient implementation of the demodulation and decoding circuitry for FeliCa coded signals. The digital part handles the FeliCa framing and error detection like CRC. The CLRC663 supports contactless communication using FeliCa Higher transfer speeds up to 424 kbit/s in both directions. The CLRC663 supports vicinity protocol according to ISO/IEC15693, EPC UID and ISO/IEC 18000-3 mode 3. The complete vicinity product family of NXP is supported and enable a readability for mid-ranger reader applications. The following host interfaces are provided: Serial Peripheral Interface (SPI) Serial UART (similar to RS232 with voltage levels dependent on pin voltage supply) 2 I C-bus interface (two versions are implemented: I2C and I2CL) 2.2 LPC1227 The LPC1227 are ARM Cortex-M0-based microcontrollers for embedded applications featuring a high level of integration and low-power consumption. The ARM Cortex-M0 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration. In addition to the ARM Cortex-M0, the LPC1X features an event handler API to limit the interrupt load of the ARM Cortex-M0 CPU and to allow for additional power-savings by off-loading event handling from the main CPU. The LPC1227 operates at CPU frequencies of up to 33 MHz and include up to 128 kB of flash memory and 8 kB of data memory. Not all connections of the LPC1227 product are implemented by the PR601. 3. Features and benefits Fully compliant with ISO/IEC 14443 A and B, ISO/IEC 15693 and FeliCa Support for MIFARE technology NFC-IP1 peer-to-peer support (Passive Initiator Mode) Compatibility with all established smartcard ICs, smart tags, and label technologies Support for SAM AV 2.6 interface PR601 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 3.0 12 November 2012 COMPANY PUBLIC 219330 2 of 14