S912XEQ512J3MAA NXP

MC9S12XEP100 Reference Manual Covers MC9S12XE Family HCS12X Microcontrollers MC9S12XEP100RMV1 Rev. 1.25 02/2013 freescale.comTo provide the most up-to-date information, the document revision on the World Wide Web is the most current. A printed copy may be an earlier revision. To verif, refer to: freescale.com This document contains information for the complete S12XE-Family and thus includes a set of separate FTM module sections to cover the whole family. A full list of family members and options is included in the appendices. This document contains information for all constituent modules, with the exception of the S12X CPU. For S12X CPU information please refer to CPU12XV2 in the CPU12/CPU12X Reference Manual. Revision History. Refer to module section revision history tables for more information. Date Revision Description Updated NVM timing parameter section for brownout case Specied time delay from RESET to start of CPU code execution Sep, 2008 1.18 Added NVM patch Part IDs Enhanced ECT GPIO / timer function transitioning description Updated 208MAPBGA thermal parameters Revised TIM ag clearing procedure Dec, 2008 1.19 Corrected CRG register address Added maskset identier sufx for ATMC fab Fixed typos Added 208MAPBGA disclaimer Aug, 2009 1.20 Added VREAPI to PT5. Added LVR Note to electricals. Updates to TIM/ECT/XGATE/SCI/MSCAN (see embedded rev. history) FTM section (see FTM revision history) Apr, 2010 1.21 PIM section (see PIM revision history) ECT and TIM sections (see ECT, TIM revision history tables) May, 2010 1.22 BDM Alternate clock source dened in device overview Sep, 2010 1.23 Added S12XEG256 option. Updated MSCAN section Added bandgap voltage to electricals Added new maskset and Part ID numbers Aug, 2012 1.24 Minor updates to MSCAN,SCI and S12XINT sections Removed BGA disclaimer Updated MSCAN section Feb, 2013 1.25 Formatting updates and minor corrections in PWM, CRG, BDM, DBG sections Updated Ordering Information