SAF784x One chip CD audio device with integrated MP3/WMA decoder Rev. 02 9 May 2008 Product data sheet 1. General description The SAF784x is a single-chip solution CD audio decoder with on-chip MP3 and WMA decoding, digital servo, audio DAC, sample-rate converter, preamplier, laser driver and integrated ARM7TDMI-S microprocessor. The device contains all of the required ROM and RAM, including an internal re-programmable Flash ROM, and is targeted at low-cost compressed audio CD applications. The design is a one-chip CD audio decoder IC, with additions to allow low-cost system implementation of MP3 and WMA decoding. 2. Features 2.1 Features n Channel decoder and digital servo n 32-bit embedded ARM7 RISC microprocessor supporting both 32-bit and 16-bit (Thumb) instruction sets n Maximum ARM operating frequency of 76 MHz, equivalent to 68 MIPS n Decoding of compressed audio stream (MP3/WMA) on ARM7 core n All memories required for MP3/WMA decoding embedded on chip: combination of 130 kB mask-programmed internal program ROM (to reduce wait-states on high-speed code, e.g. decompression algorithms), 42 kB boot ROM, 64 kB of internal re-programmable Flash ROM (for simple re-programming of application code) 110 kB internal SRAM n Programmable clock frequency for ARM microprocessor - allowing users to trade-off power consumption and processing power depending on requirements n Block decoder hardware to perform C3 error correction n Sample-rate converter circuit to convert compressed audio sample rates (in the range 8 kHz to 48 kHz) to an output rate of 44.1 kHz n Microprocessor access to digital representations of the diode input signals from the optical pickup the microprocessor can also generate the servo output signals RA, FO, SL, allowing the possibility of additional servo algorithms in software n Programmable PDM outputs (effectively sine and cosine) to allow use of stepper motor for sledge mechanism n Microprocessor access to audio streams, both from the internal CD decoder and an external stereo auxiliary input (e.g. an analog source from a tuner, converted to digital via on-chip ADCs) to allow audio processing algorithms in the ARM microprocessor, e.g. bass boost, volume control n Four general-purpose analog inputs (A IN1 to A IN4) allowing the ARM microprocessor access to other external analog signals, e.g. low-cost keypad, temperature sensor, via on-chip ADCsSAF784x NXP Semiconductors One chip CD audio device with integrated MP3/WMA decoder n Two additional analog audio inputs (AUX L, AUX R) to allow the ARM microprocessor access to external audio signals (e.g. tuner) allows audio algorithms (e.g. bass boost) to be performed on external audio signals n Real-time clock operated from separate 32 kHz crystal allows low-power Standby mode with real-time clock still operational n Watchdog timer 2 n I S-bus, S/PDIF, subcode (V4) and subcode sync outputs n 32 GPIOs n Two standard UART channels n Two external interrupt pins 2 n I C-bus interface congurable for master or slave modes, supporting 100 kbit/s and 400 kbit/s standards 2 n Slave I S-bus mode, in which the channel decoder can synchronize the CD playback 2 speed to an I S-bus clock input n Integrated digital HF/Mirror detector with measurement of minimum and maximum peak values, amplitude and offset n Integrated CD-text decoder n Up to 6 decode speed, CLV or CAV modes n LQFP144 package with 0.5 mm pin pitch n Separate left and right channel digital silence detection available on KILL pins n Digital silence detection available on loopback data from external source as well as internal data n Filterless pseudo bit stream audio DAC with minimal external components n Stereo line outputs for audio DAC 2 n Loopback mode allowing the use of integrated DAC with external I S-bus/EIAJ sources n Compatible with voltage mode mechanisms n On-chip buffering and ltering of the diode signals from the mechanism in order to optimize the signals for the decoder and servo parts n LF (servo) signals converted to digital representations by Sigma-Delta ADCs shared between pairs of channels to minimize DC offset between channels n HF part summed from signals D1 to D4 and converted to digital signals by HF 6-bit ADC n Selectable DC offset cancellation of quiescent mechanism voltages and dark currents, digitally controlled additional ne DC-offset cancellation in digital domain n Eye pattern monitor system to observe selectable points within the analog pre-amp n Current and average jitter values available via registers n On-chip laser power control, up to maximum currents of 120 mA n Laser on-off control, including soft-start control - zero-to-nominal output power in 1ms n Monitor control and feedback circuit to maintain nominal output power throughout laser life n Congured for Nsub (N-substrate) monitor diode n JTAG interface for device access and ARM code development (compatible with ARM multi-ICE) n All digital input pins 5 V tolerant n Low-latency static memory interface to access a maximum of two 2 MB memory SAF784X 2 NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 9 May 2008 2 of 93