SC18IS600IPW/S8HP NXP

SC18IS600 2 SPI to I C-bus interface Rev. 8 9 October 2019 Product data sheet 1. General description The SC18IS600 is designed to serve as an interface between the standard SPI of a host 2 (microcontroller, microprocessor, chip set, etc.) and the serial I C-bus. This allows the 2 host to communicate directly with other I C-bus devices. The SC18IS600 can operate as 2 2 an I C-bus master-transmitter or master-receiver. The SC18IS600 controls all the I C-bus specific sequences, protocol, arbitration and timing. 2. Features and benefits SPI slave interface SPI Mode 3 2 Single master I C-bus controller Four General Purpose Input/Output (GPIO) pins Two quasi-bidirectional I/O pins 5 V tolerant I/O pins High-speed SPI: Up to 1.2 Mbit/s 2 High-speed I C-bus: 400 kbit/s 96-byte transmit buffer 96-byte receive buffer 2.4 V to 3.6 V operation Power-down mode with WAKEUP pin Internal oscillator Active LOW interrupt output Available in TSSOP16 packageSC18IS600 NXP Semiconductors 2 SPI to I C-bus interface 3. Ordering information Table 1. Ordering information Type number Topside Package marking Name Description Version SC18IS600IPW/S8 18IS600 TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 3.1 Ordering options Table 2. Ordering options Type number Orderable part number Package Packing method Minimum Temperature order quantity 1 SC18IS600IPW/S8 SC18IS600IPW/S8HP TSSOP16 REEL 13 Q4/T2 2500 T = 40 C to +85 C amb *STANDARD MARK SMD 1 NXP plans to supply the /S8 device with an expected discontinuation in the 2024-2025 timeframe, but in the meantime, Failure Analysis for /S8 devices will consist of Automated Test Equipment (ATE) and electrical overstress verification along with package and wire bond validation only. Detailed device failure analysis will not be available refer to CIN 201708035I. SC18IS600 All information provided in this document is subject to legal disclaimers. NXP B.V. 2019. All rights reserved. Product data sheet Rev. 8 9 October 2019 2 of 28