INTEGRATED CIRCUITS SC28L194 Quad UART for 3.3 V and 5 V supply voltage Product data sheet 2006 Aug 15 Supersedes data of 2001 Feb 13 IC19 Data Handbook Philips Semiconductors Product data sheet Quad UART for 3.3 V and 5 V supply voltage SC28L194 DESCRIPTION FEATURES The Philips 28L194 Quad UART is a single chip CMOS-LSI Single 3.3V and 5.0V power supply communications device that provides 4 full-duplex asynchronous Four Philips industry standard full duplex UART channels channels with significantly deeper 16 byte FIFOs, Automatic in-band Sixteen byte receiver FIFOs for each UART flow control using Xon/Xoff characters defined by the user and address recognition in the Wake-up mode. Synchronous bus Sixteen byte transmit FIFOs for each UART interface is used for all communication between host and QUART. It In band flow control using programmable Xon/Xoff characters is fabricated in Philips state of the art CMOS technology that Flow control using CTSN RTSN hardware handshaking combines the benefits of low cost, high density and low power consumption. Automatic address detection in multi-drop mode Three byte general purpose character recognition The operating speed of each receiver and transmitter can be selected independently from one of 22 fixed baud rates, a 16X clock Fast data bus, 15 ns data bus release time, 125 ns bus cycle time derived from one of two programmable baud rate counters or one of Programmable interrupt priorities three external 16X clocks (1 available at 1x clock rate). The baud Automatic identification of highest priority interrupt pending rate generator and counter can operate directly from a crystal or from seven other external or internal clock inputs. The ability to Global interrupt and control registers ease setup and interrupt handling independently program the operating speed of the receiver and transmitter makes the Quad UART particularly attractive for dual Vectored interrupts with programmable interrupt vector formats speed full duplex channel applications such as clustered terminal Interrupt vector modified with channel number systems. The receivers and transmitters are buffered with FIFOs of Interrupt vector modified with channel number and channel type 16 characters to minimize the potential for receiver overrun and to Interrupt vector not modified reduce interrupt overhead. In addition, a handshaking capability and in-band flow control are provided to disable a remote UART IACKN and DACKN signal pins transmitter when the receiver buffer is full or nearly so. Watch dog timer for each receiver (64 receive clock counts) To minimize interrupt overhead an interrupt arbitration system is Programmable Data Formats: included which reports the context of the interrupting UART via 5 to 8 data bits plus parity direct access or through the modification of the interrupt vector. The Odd, even force or no parity context of the interrupt is reported as channel number, type of 1, 1.5 or 2 stop bits device interrupting (receiver COS etc.) and, for transmitters or receivers, the fill level of the FIFO. Flexible baud rate selection for receivers and transmitters: 22 fixed rates 50 - 230.4K baud or 100 to 460.8K baud The Quad UART provides a power down mode in which the oscillator is stopped but the register contents are maintained. This Additional non-standard rates to 500K baud with internal results in reduced power consumption of several orders of generators magnitudes. The Quad UART is fully TTL compatible when Two reload-counters provide additional programmable baud operating from a single +5V or 3.3V power supply. Operation at 3.3V rate generation or 5.0V is maintained with CMOS interface levels. External 1x or 16x clock inputs Simplified baud rate selection Uses Statistical Multiplexers 1 MHz 1x and 16x data rates full duplex all channels. Parity, framing and overrun error detection Data Concentrators Packet-switching networks False start bit detection Process Control Line break detection and generation Building or Plant Control Programmable channel mode Laboratory data gathering Normal(full duplex) ISDN front ends Diagnostic modes Computer Networks automatic echo Point-of-Sale terminals local loop back Automotive, cab and engine controls remote loop back Entertainment systems Four I/O ports per UART for modem controls, clocks, RTSN, I/O, MIDDI keyboard control music systems etc. All I/O ports equipped with Change of State Detectors Theater lighting control Two global inputs and two global outputs for general purpose I/O Terminal Servers Computer-Printer/Plotter links Power down mode On chip crystal oscillator, 2-8 MHz TTL input levels. Outputs switch between full V and V CC SS High speed CMOS technology 80-pin Low Profile Quad Flat Pack LQFP and 68-pin PLCC 2 2006 Aug 15