SC28L92 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter (DUART) Rev. 07 19 December 2007 Product data sheet 1. General description The SC28L92 is a pin and function replacement for the SCC2692 and SC26C92 operating at 3.3 V or 5 V supply with added features and deeper FIFOs. Its conguration on power-up is that of the SC26C92. Its differences from the SCC2692 and SC26C92 are: 16 character receiver, 16 character transmit FIFOs, watchdog timer for each receiver, mode register 0 is added, extended baud rate and overall faster speeds, programmable receiver and transmitter interrupts. (Neither the SC26C92 nor the SCC2692 is being discontinued.) Pin programming will allow the device to operate with either the Motorola or Intel bus interface. The bit 3 of the MR0A register allows the device to operate in an 8 byte FIFO mode if strict compliance with the SC26C92 FIFO structure is required. The NXP Semiconductors SC28L92 Dual Universal Asynchronous Receiver/Transmitter (DUART) is a single-chip CMOS-LSI communications device that provides two full-duplex asynchronous receiver/transmitter channels in a single package. It interfaces directly with microprocessors and may be used in a polled or interrupt driven system with modem and DMA interface. The operating mode and data format of each channel can be programmed independently. Additionally, each receiver and transmitter can select its operating speed as one of 28 xed baud rates a 16 clock derived from a programmable counter/timer, or an external 1 or 16 clock. The baud rate generator and counter/timer can operate directly from a crystal or from external clock inputs. The ability to independently program the operating speed of the receiver and transmitter make the DUART particularly attractive for dual-speed channel applications such as clustered terminal systems. Each receiver and transmitter is buffered by 8 or 16 character FIFOs to minimize the potential of receiver overrun, transmitter underrun and to reduce interrupt overhead in interrupt driven systems. In addition, a ow control capability is provided via RTS/CTS signaling to disable a remote transmitter when the receiver buffer is full. Also provided on the SC28L92 are a multipurpose 7-bit input port and a multipurpose 8-bit output port. These can be used as general purpose I/O ports or can be assigned specic functions (such as clock inputs or status/interrupt outputs) under program control. The SC28L92 is available in three package versions: PLCC44, QFP44, and HVQFN48.SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 2. Features n Member of IMPACT family: 3.3 V to 5.0 V, - 40 C to +85 C and 68xxx or 80xxx bus interface for all devices n Dual full-duplex independent asynchronous receiver/transmitters n 16 character FIFOs for each receiver and transmitter n Pin programming selects 68xxx or 80xxx bus interface n Programmable data format u 5 data to 8 data bits plus parity u Odd, even, no parity or force parity 1 u 1 stop, 1.5 stop or 2 stop bits programmable in -bit increments 16 n 16-bit programmable counter/timer n Programmable baud rate for each receiver and transmitter selectable from: u 28 xed rates: 50 kBd to 230.4 kBd u Other baud rates to 1 MHz at 16 u Programmable user-dened rates derived from a programmable counter/timer u External 1 or 16 clock n Parity, framing, and overrun error detection n False start bit detection n Line break detection and generation n Programmable channel mode u Normal (full-duplex) u Automatic echo u Local loopback u Remote loopback u Multi-drop mode (also called wake-up or 9-bit) n Multi-function 7-bit input port (includes IACKN) u Can serve as clock or control inputs u Change of state detection on four inputs u Inputs have typically > 100 k pull-up resistors u Change of state detectors for modem control n Multi-function 8-bit output port u Individual bit set/reset capability u Outputs can be programmed to be status/interrupt signals u FIFO status for DMA interface n Versatile interrupt system u Single interrupt output with eight maskable interrupting conditions u Output port can be congured to provide a total of up to six separate interrupt outputs that may be wire ORed u Each FIFO can be programmed for four different interrupt levels u Watchdog timer for each receiver n Maximum data transfer rates: 1 - 1 Mbit/s, 16 - 1 Mbit/s n Automatic wake-up mode for multi-drop applications n Start-end break interrupt/status n Detects break which originates in the middle of a character SC28L92 7 NXP B.V. 2007. All rights reserved. Product data sheet Rev. 07 19 December 2007 2 of 73