SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs and 68 mode P interface Rev. 04 20 January 2010 Product data sheet 1. General description The SC68C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s. The SC68C752B offers enhanced features. It has a Transmission Control Register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during hardware and software flow control. With the FIFO Rdy register, the software gets the status of TXRDYn/RXRDYn for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows on-board diagnostics. The UART transmits data, sent to it over the peripheral 8-bit bus, on the TXn signal and receives characters on the RXn signal. Characters can be programmed to be 5 bits, 6 bits, 7 bits, or 8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing errors, FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control operations, and has software flow control and hardware flow control capabilities. The SC68C752B is available in LQFP48 and HVQFN32 packages. 2. Features Dual channel with 68 mode (Motorola) P interface Up to 5 Mbit/s data rate 64-byte transmit FIFO 64-byte receive FIFO with error flags Programmable and selectable transmit and receive FIFO trigger levels for DMA and interrupt generation Software/hardware flow control Programmable Xon/Xoff characters Programmable auto-RTS and auto-CTS Optional data flow resume by Xon any character DMA signalling capability for both received and transmitted data Supports 5 V, 3.3 V and 2.5 V operationSC68C752B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 1 5 V tolerant on input only pins Software selectable baud rate generator Prescaler provides additional divide-by-4 function Industrial temperature range (40 C to +85 C) Fast data bus access time Programmable Sleep mode Programmable serial interface characteristics 5-bit, 6-bit, 7-bit, or 8-bit characters Even, odd, or no parity bit generation and detection 1, 1.5, or 2 stop bit generation False start bit detection Complete status reporting capabilities in both normal and Sleep mode Line break generation and detection Internal test and loopback capabilities Fully prioritized interrupt system controls Modem control functions (CTS, RTS, DSR, DTR, RI, and CD) 3. Ordering information Table 1. Ordering information Type number Package Name Description Version SC68C752BIB48 LQFP48 plastic low profile quad flat package 48 leads SOT313-2 body 7 7 1.4 mm SC68C752BIBS HVQFN32 plastic thermal enhanced very thin quad flat package SOT617-1 no leads 32 terminals body 5 5 0.85 mm 1. For data bus pins D7 to D0, see Table 25 Limiting values. SC68C752B 4 NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 20 January 2010 2 of 48