SDIO101 SD/SDIO/MMC/CE-ATA host controller Rev. 5 22 August 2011 Product data sheet 1. General description The SDIO101 is a SD/SDIO/MMC/CE-ATA host controller with a standard 16-bit asynchronous memory interface. The device conforms to the SD Host Standard Specification Version 2.0 (see Ref. 1). The SDIO101 manages the physical layer of SD, SDIO, MMC and CE-ATA protocols and can be used together with SD Host Standard compatible driver software to add SD/SDIO/MMC/CE-ATA host functionality to a variety of microprocessor systems. The SDIO101 supports both full-speed (< 25 MHz) and high-speed (< 52 MHz) data transmissions on the SD/SDIO/MMC/CE-ATA port. The SDIO101 offers separate pins for SD/SDIO/MMC/CE-ATA port supply voltage, host interface supply voltage and core supply voltage. The SD/SDIO/MMC/CE-ATA port can operate at a wide voltage range (1.8 V to 3.6 V) which allows the device to interface to a large variety of SD, SDIO, MMC or CE-ATA devices. The SDIO101 allows 1-bit and 4-bit SD transactions and 8-bit MMC/CE-ATA transactions. The 16-bit asynchronous memory interface can operate at a 2.5 V to 3.6 V voltage range. A built-in, 2 kB data buffer allows for a low interrupt latency time and efficient communication with the host processor at high data rates. The SDIO101 provides a DMA request line that can be connected to an external DMA controller to off-load the host processor and increase overall system performance. An on-board PLL allows a large range of SD/SDIO/MMC/CE-ATA clock speeds to be generated from a single externally available clock source. An additional fractional divider allows the SD clock speed to be fine-tuned with very fine granularity, which enables the user to achieve the maximum desired SD clock speed from the external clock source. The SDIO101 offers 5 levels of power saving, including a Hibernate mode where the on-board oscillator, PLL and data buffer memories are switched off, and a Coma mode in which supply power to most of the device is internally switched off. This allows the device to be used in very power-critical applications. 2. Features and benefits 2.1 General Provides 1 SD/SDIO/MMC/CE-ATA slot, operating in 1-bit, 4-bit and 8-bit (MMC/CE-ATA) modes 2.5 V to 3.3 V host interface 1.8 V core supply voltage Separate SD supply voltage pin. SD/SDIO/MMC/CE-ATA slot is able to operate at a wide voltage range (1.8 V to 3.3 V).SDIO101 NXP Semiconductors SD/SDIO/MMC/CE-ATA host controller Compliant with SDIO card specification version 2.00 (see Ref. 2) Compliant with SD Host Controller Standard Specification Version 2.0 (see Ref. 1) Compliant with SD Physical Layer Specification version 2.0 (see Ref. 3) Compliant with MMC Specification version 3.31 and 4.2 (see Ref. 4) Supports CE-ATA Digital Protocol revision 1.1 (see Ref. 5) Supports CE-ATA Digital Protocol commands (CMD60/CMD61) Dedicated SD Card Detection input pin (insertion/removal) Dedicated SD Card Write Protection input pin Full speed (< 25 MHz) and high-speed (< 52 MHz) SD data transmissions Supports interrupt and slave-DMA transfer operation Built-in 2 kB double data buffer (with 1 kB maximum block size) for efficient communication with host processor Supports SDIO features Multi-block, Suspend/Resume, Read Wait and Wake-up Control Up to 400 Mbit/s read and write data transfer rates at 50 MHz using MMC 8 data lines Up to 208 Mbit/s read and write data transfer rates at 52 MHz using SD 4 data lines On-board crystal oscillator and PLL 5 levels of power saving, including a Hibernate mode where oscillator, PLL and memories are switched off, and a Coma mode that internally switches off supply power to most of the chip Additional on-board fractional clock divider for fine-grained SD clock speed control Cyclic Redundancy Check (CRC) for command and data Programmable pull-up resistor on SD CMD and SD DATn lines Programmable drive strength for SDCLK output to optimize SD/SDIO/MMC/CE-ATA clock speed 2.2 Host processor interface Supports 16-bit asynchronous memory interface Separate host interface power supply pin, able to operate on 2.5 V to 3.3 V Programmable open collector or push-pull mode for INT interrupt pin output 3. Ordering information Table 1. Ordering information Type number Package Name Description Version SDIO101IHR HXQFN60U plastic thermal enhanced extremely thin quad flat SOT1133-1 package no leads 60 terminals UTLP based body 5 5 0.5 mm SDIO101 All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 22 August 2011 2 of 38