SPC5601DF1VLL4 NXP

Freescale Semiconductor Document Number: MPC5602D Rev. 6, 01/2013 Data Sheet: Technical Data MPC5602D 100 LQFP 64 LQFP 14 mm x 14 mm 10 mm x 10 mm MPC5602D Microcontroller Data Sheet Up to 79 configurable general purpose pins Single issue, 32-bit CPU core complex (e200z0h) supporting input and output operations (package Compliant with the Power Architecture dependent) embedded category Real Time Counter (RTC) with clock source from Includes an instruction set enhancement 128 kHz or 16 MHz internal RC oscillator allowing variable length encoding (VLE) for supporting autonomous wakeup with 1 ms code size footprint reduction. With the optional resolution with max timeout of 2 seconds encoding of mixed 16-bit and 32-bit Up to 4 periodic interrupt timers (PIT) with 32-bit instructions, it is possible to achieve significant counter resolution code size footprint reduction. 1 System Timer Module (STM) Up to 256 KB on-chip Code Flash supported with Flash controller and ECC Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class 1 standard 64 KB on-chip Data Flash with ECC Device/board boundary Scan testing supported with Up to 16 KB on-chip SRAM with ECC per Joint Test Action Group (JTAG) of IEEE (IEEE Interrupt controller (INTC) with multiple interrupt 1149.1) vectors, including 20 external interrupt sources and On-chip voltage regulator (VREG) for regulation of 18 external interrupt/wakeup sources input supply for all internal levels Frequency modulated phase-locked loop (FMPLL) Crossbar switch architecture for concurrent access to peripherals, Flash, or SRAM from multiple bus masters Boot assist module (BAM) supports internal Flash programming via a serial link (CAN or SCI) Timer supports input/output channels providing a range of 16-bit input capture, output compare, and pulse width modulation functions (eMIOS-lite) Up to 33 channel 12-bit analog-to-digital converter (ADC) 2 serial peripheral interface (DSPI) modules 3 serial communication interface (LINFlex) modules LINFlex 1 and 2: Master capable LINFlex 0: Master capable and slave capable connected to eDMA 1 enhanced full CAN (FlexCAN) module with configurable buffers This document contains information on a new product. Specifications and information herein are subject to change without notice. Freescale Semiconductor, Inc., 20092013. All rights reserved.Table of Contents 1 Introduction 3 4.10 Power consumption . 41 1.1 Document overview 3 4.11 Flash memory electrical characteristics 42 1.2 Description .3 4.11.1 Program/Erase characteristics . 42 2 Block diagram 4 4.11.2 Flash power supply DC characteristics 44 3 Package pinouts and signal descriptions .7 4.11.3 Start-up/Switch-off timings 45 3.1 Package pinouts .7 4.12 Electromagnetic compatibility (EMC) characteristics 45 3.2 Pad configuration during reset phases 9 4.12.1 Designing hardened software to avoid 3.3 Voltage supply pins .9 noise problems . 45 3.4 Pad types .10 4.12.2 Electromagnetic interference (EMI) . 46 3.5 System pins .10 4.12.3 Absolute maximum ratings (electrical sensitivity)46 3.6 Functional ports 11 4.13 Fast external crystal oscillator (4 to 16 MHz) electrical 4 Electrical characteristics .21 characteristics . 48 4.1 Introduction 21 4.14 FMPLL electrical characteristics . 51 4.2 Parameter classification 21 4.15 Fast internal RC oscillator (16 MHz) electrical 4.3 NVUSRO register .21 characteristics . 51 4.3.1 NVUSRO PAD3V5V field description 22 4.16 Slow internal RC oscillator (128 kHz) electrical 4.3.2 NVUSRO OSCILLATOR MARGIN field characteristics . 52 description .22 4.17 ADC electrical characteristics . 54 4.3.3 NVUSRO WATCHDOG EN field description 22 4.17.1 Introduction . 54 4.4 Absolute maximum ratings 22 4.17.2 Input impedance and ADC accuracy 55 4.5 Recommended operating conditions 23 4.17.3 ADC electrical characteristics . 60 4.6 Thermal characteristics .26 4.18 On-chip peripherals . 62 4.6.1 Package thermal characteristics 26 4.18.1 Current consumption 62 4.6.2 Power considerations 26 4.18.2 DSPI characteristics . 63 4.7 I/O pad electrical characteristics 27 4.18.3 JTAG characteristics 70 4.7.1 I/O pad types .27 5 Package characteristics 70 4.7.2 I/O input DC characteristics 27 5.1 Package mechanical data 70 4.7.3 I/O output DC characteristics .28 5.1.1 100 LQFP . 70 4.7.4 Output pin transition times .31 5.1.2 64 LQFP 74 4.7.5 I/O pad current specification .31 6 Ordering information . 77 4.8 RESET electrical characteristics 35 7 Document revision history . 78 4.9 Power management electrical characteristics 37 4.9.1 Voltage regulator electrical characteristics 37 4.9.2 Low voltage detector electrical characteristics .40 MPC5602D Microcontroller Data Sheet, Rev. 6 2 Freescale Semiconductor